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| hc705ct4grs/d rev. 2.0 non-disclosure agreement required MC68HC705CT4 general release specification september 16, 1997 csic mcu design center austin, texas f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general release specitcation general release specification MC68HC705CT4 rev. 2.0 2 motorola motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola list of sections 3 non-disclosure agreement required general release specification MC68HC705CT4 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 15 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 section 3. central processing unit . . . . . . . . . . . . . . . . . 31 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 section 6. operating modes. . . . . . . . . . . . . . . . . . . . . . 49 section 7. parallel input/output (i/o) . . . . . . . . . . . . . . 55 section 8. 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 section 9. synchronous serial interface (ssi) . . . . . . . . 69 section 10. core timer . . . . . . . . . . . . . . . . . . . . . . . . . . 79 section 11. dual phase-locked loop (pll) . . . . . . . . . . 85 section 12. pulse width modulator (pwm) . . . . . . . . . . 93 section 13. comparators . . . . . . . . . . . . . . . . . . . . . . . . 99 section 14. miscellaneous register . . . . . . . . . . . . . . . 105 section 15. eprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 section 16. instruction set . . . . . . . . . . . . . . . . . . . . . . . 117 section 17. electrical specifications . . . . . . . . . . . . . . 135 section 18. mechanical specifications . . . . . . . . . . . . 143 section 19. ordering information . . . . . . . . . . . . . . . . . 147 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required list of sections general release specification MC68HC705CT4 rev. 2.0 4 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola table of contents 5 non-disclosure agreement required general release specification MC68HC705CT4 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.4 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4.2 v dd2 and v ss2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4.3 maskable interrupt request ( irq/v pp ) . . . . . . . . . . . . . . . .20 1.4.4 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.4.5 reset ( reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.6 port a (pa0Cpa7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.7 port b (pb0Cpb7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.8 port c (pc0Cpc7/pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.9 port d (pd0/cmp3+, pd1/cmp1C, pd2/cmp12+, pd3/cmp2C, pd4/sdio, pd5/sck, and pd6/tcmp) . . . . . . . . . . . . . . . . . . . . . .22 1.4.10 tcap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.11 fint and finr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.12 pdoutt and pdoutr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 eraseable programmable read-only memory (eprom) . . . .25 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . .26 section 3. central processing unit 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required table of contents general release specification MC68HC705CT4 rev. 2.0 6 table of contents motorola 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.4 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.6 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.7 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.3 cpu interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.4 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.5 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.6 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.7 external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.8 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.9 16-bit timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.10 ssi interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.11 core timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.12 comparator 3 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.3 external reset (reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 power-on reset (por). . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2 computer operating properly reset (copr) . . . . . . . . . . .46 5.4.2.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2.2 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2.3 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2.4 cop watchdog timer considerations . . . . . . . . . . . . . . .47 5.4.2.5 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.4.3 illegal address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 section 6. operating modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC705CT4 rev. 2.0 general release specification motorola table of contents 7 non-disclosure agreement required 6.3 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4 bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5.2 stop recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.5.4 low-power wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 section 7. parallel input/output (i/o) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.7 input/output port pin programming . . . . . . . . . . . . . . . . . . . . .57 section 8. 16-bit timer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.3 counter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 8.4 output compare register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 8.5 input capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 8.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.8 timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 8.9 timer during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 8.10 timer power supply source . . . . . . . . . . . . . . . . . . . . . . . . . . .67 section 9. synchronous serial interface (ssi) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.3 signal format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.3.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.3.2 serial data in/out (sdio) . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.4 ssi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required table of contents general release specification MC68HC705CT4 rev. 2.0 8 table of contents motorola 9.4.1 ssi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.4.2 ssi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 9.4.3 ssi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 9.5 operation during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 9.6 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 9.7 ssi power supply source . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 section 10. core timer 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 10.3 core timer control and status register. . . . . . . . . . . . . . . . . .81 10.4 core timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . .83 10.5 computer operating properly (cop) reset . . . . . . . . . . . . . . .84 10.6 timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 10.7 core timer power supply source . . . . . . . . . . . . . . . . . . . . . .84 section 11. dual phase-locked loop (pll) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.3.1 dual control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.3.2 12-bit reference counter modulus register. . . . . . . . . . . .89 11.3.3 16-bit transmit counter modulus register . . . . . . . . . . . . .90 11.3.4 16-bit receive counter modulus register . . . . . . . . . . . . .91 11.4 pll power supply source . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 section 12. pulse width modulator (pwm) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12.4 pwm data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.5 pwm during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12.6 pwm during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12.7 pwm during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12.8 pwm power supply source . . . . . . . . . . . . . . . . . . . . . . . . . . .97 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC705CT4 rev. 2.0 general release specification motorola table of contents 9 non-disclosure agreement required section 13. comparators 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 13.3 comparator control/status register. . . . . . . . . . . . . . . . . . . .101 13.4 reading comparator outputs. . . . . . . . . . . . . . . . . . . . . . . . .103 13.5 comparator during wait mode . . . . . . . . . . . . . . . . . . . . . . . .103 13.6 comparator during stop mode. . . . . . . . . . . . . . . . . . . . . . . .103 13.7 comparator power supply source . . . . . . . . . . . . . . . . . . . . .103 section 14. miscellaneous register 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 14.3 miscellaneous control register . . . . . . . . . . . . . . . . . . . . . . .105 14.4 miscellaneous register power supply source . . . . . . . . . . . .106 section 15. eprom 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 15.3 eprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 15.4 bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 15.4.1 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 15.4.2 programming register . . . . . . . . . . . . . . . . . . . . . . . . . . .112 15.4.3 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 section 16. instruction set 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 16.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 16.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 16.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 16.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 16.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 16.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 16.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 16.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 16.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required table of contents general release specification MC68HC705CT4 rev. 2.0 10 table of contents motorola 16.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 16.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . .122 16.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . .123 16.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . .124 16.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .126 16.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 16.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 section 17. electrical specifications 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 17.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 17.4 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 17.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 17.6 5.0 v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . .138 17.7 3.3 v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . .139 17.8 3.3 v and 5.0 v control timing. . . . . . . . . . . . . . . . . . . . . . . .140 17.9 comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 17.10 pwm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 17.11 pll signal input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 section 18. mechanical specifications 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 18.3 44-lead plastic-leaded chip carrier (case 777-02) . . . . . . .144 18.4 44-lead quad flat pack (case 824a-01) . . . . . . . . . . . . . . .145 section 19. ordering information 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 19.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 19.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .148 19.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . .149 19.6 rom verification units (rvus) . . . . . . . . . . . . . . . . . . . . . . .150 19.7 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola list of figures 11 non-disclosure agreement required general release specification MC68HC705CT4 list of figures figure title page 1-1 MC68HC705CT4 block diagram . . . . . . . . . . . . . . . . . . . . .18 1-2 44-lead plcc pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1-3 44-lead qfp pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1-4 oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2-1 MC68HC705CT4 8-k memory map . . . . . . . . . . . . . . . . . . .27 2-2 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3-2 stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4-1 interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . .38 4-2 irq function block diagram . . . . . . . . . . . . . . . . . . . . . . . .39 5-1 reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5-2 reset and por timing diagram . . . . . . . . . . . . . . . . . . . .45 5-3 cop watchdog timer location . . . . . . . . . . . . . . . . . . . . . .48 6-1 single-chip mode pinout of the MC68HC705CT4 . . . . . . . .50 6-2 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . . .52 6-3 stop/wait flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 7-1 port c pullup option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7-2 i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 8-1 16-bit timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . .61 8-2 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . .64 8-3 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . .65 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures MC68HC705CT4 rev. 2.0 general release specification motorola list of figures 12 non-disclosure agreement required figure title page 9-1 ssi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 9-2 serial i/o port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9-3 ssi control register (scr) . . . . . . . . . . . . . . . . . . . . . . . . .73 9-4 ssi status register (ssr) . . . . . . . . . . . . . . . . . . . . . . . . . .75 9-5 ssi data register (sdr) . . . . . . . . . . . . . . . . . . . . . . . . . . .76 10-1 core timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .80 10-2 core timer control and status register (ctcsr) . . . . . . .81 10-3 core counter register (ctcr) . . . . . . . . . . . . . . . . . . . . . .83 11-1 dual pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11-2 dual pll control register . . . . . . . . . . . . . . . . . . . . . . . . . .87 11-3 12-bit reference counter (pllrc) . . . . . . . . . . . . . . . . . . .89 11-4 16-bit transmit counter (plltx) . . . . . . . . . . . . . . . . . . . . .90 11-5 16-bit receive counter (pllrx) . . . . . . . . . . . . . . . . . . . . .91 11-6 counter structure block diagram. . . . . . . . . . . . . . . . . . . . .92 12-1 pwm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12-2 pwm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12-3 pwm data register (pwmdr) . . . . . . . . . . . . . . . . . . . . . .96 13-1 comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . .100 13-2 comparator control/status register (cmpcsr) . . . . . . . .101 14-1 miscellaneous control register (miscr). . . . . . . . . . . . . .105 15-1 programmer interface to host . . . . . . . . . . . . . . . . . . . . . .109 15-2 MC68HC705CT4 bootloader flowchart . . . . . . . . . . . . . . .110 15-3 MC68HC705CT4 programming circuit . . . . . . . . . . . . . . .111 15-4 programing register (prog) . . . . . . . . . . . . . . . . . . . . . .112 15-5 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . .114 17-1 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . .142 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola list of tables 13 non-disclosure agreement required general release specification MC68HC705CT4 list of tables table title page 4-1 vector address for interrupts and reset . . . . . . . . . . . . . . . . .36 5-1 cop watchdog timer recommendations . . . . . . . . . . . . . . . .48 6-1 operating mode conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .49 7-1 i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 9-1 ssi rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 10-1 rti and cop rates at 2.048 mhz . . . . . . . . . . . . . . . . . . . . . .82 11-1 pll reference counter select . . . . . . . . . . . . . . . . . . . . . . . . .87 15-1 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 15-2 mor read/write based on mode and latch bit . . . . . . . . .115 16-1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . . .122 16-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . .123 16-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . .125 16-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . .126 16-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 16-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 16-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 19-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required list of tables general release specification MC68HC705CT4 rev. 2.0 14 list of tables motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola general description 15 non-disclosure agreement required general release specification MC68HC705CT4 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.4 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4.2 v dd2 and v ss2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4.3 maskable interrupt request ( irq/v pp ) . . . . . . . . . . . . . . . .20 1.4.4 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.4.5 reset ( reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.6 port a (pa0Cpa7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.7 port b (pb0Cpb7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.8 port c (pc0Cpc7/pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4.9 port d (pd0/cmp3+, pd1/cmp1C, pd2/cmp12+, pd3/cmp2C, pd4/sdio, pd5/sck, and pd6/tcmp) . . . . . . . . . . . . . . . . . . . . . .22 1.4.10 tcap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.11 fint and finr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4.12 pdoutt and pdoutr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705CT4 rev. 2.0 16 general description motorola 1.2 introduction the MC68HC705CT4 is a 44-pin member of the m68hc05 family that supports the cordless telephone applications. the memory map includes 5136 bytes of user eprom, 240 bytes of boot rom, and 256 bytes of ram. the mcu has three 8-bit input/output (i/o) ports: a, b, c; and one 7-bit i/o, port d. port c has pullup options and keyscan capability. the MC68HC705CT4 includes a bird core, a bird timer, a synchronous serial i/o (ssi), 16-bit timer, a dual 60-mhz phase-lock loop (pll), and an on-chip computer operating properly (cop) watchdog circuit. features of the MC68HC705CT4 include: ? low cost ? hc05 core ? 44-pin plastic leaded chip carrier (plcc) package ? 10.24-mhz on-chip crystal oscillator ? 2.048-mhz internal cpu speed ? 5136 bytes of user eprom ? 240 bytes of boot rom ? 256 bytes of on-chip ram ? 16-bit timer ? 31 bidirectional i/o lines ? power-saving stop and wait modes ? core timer ? dual 60-mhz pll ? simple serial with bidirectional data (ssi) ? keyscan interrupt with pullups on port c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mask options MC68HC705CT4 rev. 2.0 general release specification motorola general description 17 non-disclosure agreement required ? mask options: C cop watchdog timer C edge-sensitive or edge- and level-sensitive interrupt trigger C port c pullups for keyscan C 1-channel, 6-bit pulse width modulator (pwm) ? three comparators ? eprom security feature 1.3 mask options the mask options on the MC68HC705CT4 are handled by the eight eprom bit mask option register (mor). these options are: ? six port c pullups ? the irq sensitivity ? cop enable/disable note: rom versions of this device will have these options programmed by the factory. note: a line over a signal name indicates an active-low signal. for example, reset is active low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705CT4 rev. 2.0 18 general description motorola figure 1-1. MC68HC705CT4 block diagram osc1 osc2 reset irq/v pp cop cpu m68hc705 cpu alu cpu registers control port a data direction register pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 oscillator ram 256 bytes eprom 5136 bytes system v dd v ss accumulator index register stack pointer program counter condition code reg port c data direction register pc0 pc1 pc2 pc3 pc4 pc5 pc6 port b data direction register pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 ? 5 rx pll synth 16-bit timer system keyboard system internal processor clock rxpdout finr tx pll synth txpdout fint v dd2 v ss2 tcap 60-mhz dual pll port d data direction register pd1/cmp1C pd2/cmp12+ pd3/cmp2C pd4/sdio pd5/sck core timer system ssi comparators pwm 10.24 mhz pd6/tcmp pc7/pwm pd0/cmp3+ ? 40 boot rom 240 bytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mask options MC68HC705CT4 rev. 2.0 general release specification motorola general description 19 non-disclosure agreement required figure 1-2. 44-lead plcc pinout figure 1-3. 44-lead qfp pinout 34 39 pc1 pc2 pc3 pc4 pc5 pc6 pc7/pwm osc2 osc1 pd3/cmp2C 29 pd2/cmp12+ 7 12 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pb3 pb4 17 pb5 pb6 18 23 28 640 1 reset irq/v pp pa4 pa5 pa7 v ss v dd pd6/tcmp pd5/sck pa6 pd1/cmp1C pd0/cmp3+ v ss2 finr pdoutr pb7 pdout v dd2 pd4/sdio pc0 tcap fint 1 2 3 4 5 6 7 8 9 10 11 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pb3 pb4 pb5 pb6 44 43 42 41 40 39 38 37 36 35 34 pa4 pa5 pa6 pa7 irq/v pp reset v ss v dd pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 tcap pd6/tcmp pd5/sck pd4/sdio pd3/cmp2C pd2/cmp12+ 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 pb7 pd1/cmp1C pd0/cmp3+ osc2 osc1 v ss2 finr pdoutr pdoutt fint v dd2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705CT4 rev. 2.0 20 general description motorola 1.4 signal description the following paragraphs describe the signals. 1.4.1 v dd and v ss power is supplied to the microcontrollers digital circuits using these two pins. v dd is the positive supply and v ss is ground. 1.4.2 v dd2 and v ss2 power is supplied to noise-susceptible circuitry such as the phase- locked loop (pll), comparators, and oscillators that require cleaner supplies using these two pins. v dd2 is the positive supply and v ss2 is ground. 1.4.3 maskable interrupt request ( irq/v pp ) this pin supplies the eprom with the required programming voltage. in addition, this pin has a mask option as specified by the user that provides one of two different choices of interrupt triggering sensitivity. the options are: 1. negative edge-sensitive triggering only 2. both negative edge-sensitive and level-sensitive triggering the microcontroller unit (mcu) completes the current instruction before it responds to the interrupt request. when irq goes low for at least one t ilih , a logic 1 is latched internally to signify that an interrupt has been requested. when the mcu completes its current instruction, the interrupt latch is tested. if the interrupt latch contains a logic 1 and the interrupt mask bit (i bit) in the condition code register is clear, the mcu then begins the interrupt sequence. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for wire-or operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description signal description MC68HC705CT4 rev. 2.0 general release specification motorola general description 21 non-disclosure agreement required the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. note: the voltage on the irq pin affects the mode of operation. see section 6. operating modes . caution: port c interrupt is an external interrupt provided by port c that is generated when the part comes out of reset. therefore, an interrupt is pending that is not being serviced until the cli instruction is executed. this interrupt is produced because the state of mask option register (mor) is not known until a few clock cycles after the part comes out of reset. after this interrupt occurs, normal operation resumes, unless the part is put in reset again. 1.4.4 osc1 and osc2 these pins provide control input for an on-chip clock oscillator circuit that drives the pll reference source. a crystal resonator, a ceramic resonator, or an external signal connects to these pins providing a system clock. the oscillator frequency is selectable between 5 or 40 times the internal bus rate. typical oscillator configurations and component values are shown in figure 1-4 . the manufacturer of the crystal should be consulted, since actual component values are dependent on the type of crystal used. figure 1-4. oscillator connections < osc1 osc2 osc1 osc2 mcu mcu external clock unconnected (a) crystal/ceramic resonator (b) external clock source 10 m w 10.24 mhz oscillator connections connections 15 pf 15 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705CT4 rev. 2.0 22 general description motorola 1.4.5 reset ( reset) this active-low pin is used to reset the mcu to a known startup state by pulling reset low. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. see section 5. resets . 1.4.6 port a (pa0Cpa7) these eight i/o lines comprise port a. the state of any pin is software programmable, and all port a lines are configured as input during power- on or reset. 1.4.7 port b (pb0Cpb7) these eight i/o lines comprise port b. the state of any pin is software programmable and all port b lines are configured as input during power- on or reset. 1.4.8 port c (pc0Cpc7/pwm) these eight i/o lines comprise port c. all port c lines are configured as input during power-on or reset. port c has pullup devices and interrupt capability by pin; however, the state of any pin is determined by the user at the time of code submission. for a detailed description of i/o programming, refer to 7.7 input/output port pin programming . pc7 is shared with the output of the pulse-width modulation (pwm) function. 1.4.9 port d (pd0/cmp3+, pd1/cmp1C, pd2/cmp12+, pd3/cmp2C, pd4/sdio, pd5/sck, and pd6/tcmp) these seven port lines comprise port d. the state of any pin is software programmable and the lines are configured as input during power-on or reset. pd4 and pd5 are shared with the ssi subsystem, pd6 is shared with the 16-bit timer subsystem, and pd0Cpd3 are shared with the comparators. for a detailed description on i/o programming, refer to 7.7 input/output port pin programming . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description signal description MC68HC705CT4 rev. 2.0 general release specification motorola general description 23 non-disclosure agreement required 1.4.10 tcap this pin is used for the16-bit timer input capture operation. depending on the value of the iedg bit in the timer control register (tcr), the appropriate level of transition on tcap will be monitored. when the correct level of transition has occurred, the free-running counter will be transferred to the input capture register. 1.4.11 fint and finr these pins are inputs to the pll transmit and the receive counters, respectively. they typically are driven by the loop vco and are also ac- coupled. the minimum input signal level is 200 mv peak to peak @ 60.0 mhz. 1.4.12 pdoutt and pdoutr these pll pins are 3-state outputs of the transmit and receive phase detectors, respectively, for use as either loop error signals or phase detector signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705CT4 rev. 2.0 24 general description motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola memory 25 non-disclosure agreement required general release specification MC68HC705CT4 section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 eraseable programmable read-only memory (eprom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . .26 2.2 introduction this section describes the organization of the on-chip memory. the MC68HC705CT4 8-kbyte memory map is shown in figure 2-1 and the input/output (i/o) registers in figure 2-2 . 2.3 memory map the MC68HC705CT4 has an 8-kbyte memory map consisting of user eraseable programmable read-only memory (eprom), random-access memory (ram), bootloader rom, and i/o. 2.4 eraseable programmable read-only memory (eprom) the user eprom consists of 5120 bytes of eprom located from $0b00 to $1eff and 16 bytes of user vectors located from $1ff0 to $1fff. the bootloader rom and vectors are located from $1f01 to $1fef. twelve of the user vectors, $1ff4C$1fff, are dedicated to reset and interrupt vectors. the four remaining locations $1ff0, $1ff1, $1ff2, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required memory general release specification MC68HC705CT4 rev. 2.0 26 memory motorola and $1ff3 are general-purpose user eprom locations. location $1f00 is the mask option register (mor). the contents of the eprom cannot be prevented from being viewed externally, since security is not incorporated into the MC68HC705CT4. 2.5 random-access memory (ram) the user ram consists of 256 bytes of a shared stack area. the ram starts at address $0030 and ends at address $012f. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram in the range $00ff to $00c0. note: using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory random-access memory (ram) MC68HC705CT4 rev. 2.0 general release specification motorola memory 27 non-disclosure agreement required figure 2-1. MC68HC705CT4 8-k memory map i/o 35 bytes ram 208 bytes stack 64 bytes unused 2512 bytes user eprom 5120 bytes eprom user vectors 16 bytes $0000 $0022 $0023 $00c0 $00ff $0aff $0b00 $1fef $1ff0 $1fff ports 8 bytes core timer 2 bytes timer 10 bytes pll 8 bytes reserved port a data register port b data register port c data register port d data register port a data direction register port b data direction register port c data direction register port d data direction register core timer control/status register ssi control register ssi data register core timer counter register pll control register tx pll msb tx pll lsb rx pll msb rx pll lsb eprom programming register timer control register timer status register input capture msb input capture lsb output compare msb output compare lsb counter msb counter lsb alternate counter msb alternate counter lsb ssi status register pll ref. counter msb pll ref. counter lsb reserved eprom programming 1 byte $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f $0000 ssi 3 bytes $1eff $1f00 boot rom 240 bytes $0130 ram 48 bytes reserved 13 bytes $0030 pwm data register comparator control/status register $20 $21 $22 miscellaneous $0022 pwm 1 byte 1 byte miscellaneous register comparators 1 byte $002f $0100 $012f $1f01 mask option register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required memory general release specification MC68HC705CT4 rev. 2.0 28 memory motorola addr register name bit 7 6543210 $00 port a data register $01 port b data register $02 port c data register $03 port d data register 0 $04 port a data direction register $05 port b data direction register $06 port c data direction register $07 port d data direction register 0 $08 timer control and status register ctof rtif tofe rtie tofc rtfc rt1 rt0 $09 timer counter register $0a pll control register 0 tlock rlock refon txon rxon pls1 pls0 $0b pll reference counter msb 0000 $0c pll reference counter lsb $0d pll transmit counter msb $0e pll transmit counter lsb $0f pll receive counter msb $10 pll receive counter lsb $11 programming register moron eptst mbe ts1 ts0 latch 0 epgm $12 timer control register icie ocie toie 0 0 ton iedge olvl $13 timer status register icf ocf 0 0 0 0 0 0 $14 timer input capture msb $15 timer input capture lsb $16 timer output compare msb $17 timer output compare lsb $18 timer counter msb $19 timer counter lsb $1a timer alternate counter msb $1b timer alternate counter lsb figure 2-2. i/o registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory random-access memory (ram) MC68HC705CT4 rev. 2.0 general release specification motorola memory 29 non-disclosure agreement required $1c ssi status register sf dcol 0 0 0 0 0 0 $1d ssi data register $1e ssi control register sie se lsbf mstr cpol t/r sr1 sr0 $1f mask option register pc7pu pc6pu pc5pu pc4pu pc23pu pc01pu irq cop $20 pwm data register 00 $21 miscellaneous register 0 0 0 0 speed coe pwme 0 $22 comparator control/status register cmp3 cmp2 cmp1 cm3ie cm3ic cen3 cen2 cen1 addr register name bit 7 6543210 figure 2-2. i/o registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required memory general release specification MC68HC705CT4 rev. 2.0 30 memory motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola central processing unit 31 non-disclosure agreement required general release specification MC68HC705CT4 section 3. central processing unit 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.4 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.6 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.7 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.2 introduction the mcu contains five registers as shown in figure 3-1 . the interrupt stacking order is shown in figure 3-2 . figure 3-1. programming model a 70 x 70 hinzc ccr 11 sp 70 pc 12 0 accumulator index register program counter stack pointer condition code register 0 0 0 0 0 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required central processing unit general release specification MC68HC705CT4 rev. 2.0 32 central processing unit motorola figure 3-2. stacking order 3.3 accumulator the accumulator (a) is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.4 index register the index register (x) is an 8-bit register used for the indexed addressing value to create an effective address. the index register may also be used as a temporary storage area. index register pcl accumulator condition code register pch 111 70 stack i n t e r r u p t decreasing unstack r e t u r n increasing note: since the stack pointer decrements during pushes, the pcl is stacked first, followed by pch, etc. pulling from the stack is in the reverse order. memory addresses memory addresses a 70 x 70 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit condition code register MC68HC705CT4 rev. 2.0 general release specification motorola central processing unit 33 non-disclosure agreement required 3.5 condition code register the condition code register (ccr) is a 5-bit register in which the h, n, z, and c bits are used to indicate the results of the instruction just executed, and the i bit is used to enable interrupts. these bits can be tested individually by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) when this bit is set, the timer and external interrupt are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the i bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit also is affected during bit test and branch instructions and during shifts and rotates. hinzc ccr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required central processing unit general release specification MC68HC705CT4 rev. 2.0 34 central processing unit motorola 3.6 stack pointer the stack pointer contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer then is decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the seven most significant bits (msb) are permanently set to 0000011. these seven bits are appended to the six least significant register bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 3.7 program counter (pc) the program counter is a 13-bit register that contains the address of the next byte to be fetched. . note: the hc05 cpu core is capable of addressing 16-bit locations. for this implementation, however, the addressing registers are limited to an 8- kbyte memory map 00 00011 sp 12 7 0 pc 12 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola interrupts 35 non-disclosure agreement required general release specification MC68HC705CT4 section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.3 cpu interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.4 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.5 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.6 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.7 external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.8 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.9 16-bit timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.10 ssi interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.11 core timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.12 comparator 3 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.2 introduction the mcu can be interrupted seven different ways: 1. nonmaskable software interrupt instruction (swi) 2. external asynchronous interrupt ( irq) 3. external interrupt via irq on pc0Cpc7 4. internal 16-bit timer interrupt (timer) 5. internal synchronous serial interface (ssi) interrupt 6. internal core timer interrupt 7. comparator 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required interrupts general release specification MC68HC705CT4 rev. 2.0 36 interrupts motorola 4.3 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. if interrupts are not masked (i bit in the ccr is clear) and the corresponding interrupt enable bit is set, the processor will proceed with interrupt processing. otherwise, the next instruction is fetched and executed. if an interrupt occurs, the processor completes the current instruction, stacks the current cpu register states, sets the i bit to inhibit further interrupts, and finally checks the pending hardware interrupts. if more than one interrupt is pending after the stacking operation, the interrupt with the highest vector location shown in table 4-1 will be serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed, the cpu fetches the address of the appropriate interrupt software service routine from the vector table at locations $1ff4C$1fff as defined in table 4-1 . table 4-1. vector address for interrupts and reset register flag name interrupt cpu interrupt vector address n/a n/a reset reset $1ffeC$1fff n/a n/a software swi $1ffcC$1ffd cmcsr cmp3 cmp3, external interrupts* cmp3/irq $1ffaC$1ffb tsr ocf, icf, tof 16-bit timer interrupts timer $1ff8C$1ff9 sssr ssif ssi interrupt ssi $1ff6C$1ff7 ctcsr tofe, rtie core timer interrupts timer, rti $1ff4C$1ff5 * external interrupts include irq and portc sources. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts reset interrupt sequence MC68HC705CT4 rev. 2.0 general release specification motorola interrupts 37 non-disclosure agreement required the m68hc05 cpu does not support interruptible instructions. the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. latency = (longest instruction execution time + 10) x t cyc seconds a return-to-interrupt (rti) instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occurs during interrupt processing. 4.4 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low-level input on the reset pin or an internally generated rst signal causes the program to vector to its starting address, which is specified by the contents of memory locations $1ffe and $1fff. the i bit in the condition code register is also set. the mcu is configured to a known state during this type of reset as described in 4.3 cpu interrupt processing . 4.5 software interrupt (swi) the swi is an executable instruction and a nonmaskable interrupt since it is executed regardless of the state of the i bit in the ccr. if the i bit is zero (interrupts enabled), the swi instruction executes after interrupts that were pending before the swi was fetched or before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required interrupts general release specification MC68HC705CT4 rev. 2.0 38 interrupts motorola figure 4-1. interrupt processing flowchart n restore registers from stack: ccr, a, x, pc irq external interrupt cmp3 load pc from appropriate vector set i bit in cc register stack pc, x, a, ccr clear irq request latch fetch next instruction execute instruction n n y y y n i bit in ccr set? internal core timer interrupt swi instruction ? n y rti instruction ? y from reset y internal 16-bit timer interrupt n n y internal ssi interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts hardware interrupts MC68HC705CT4 rev. 2.0 general release specification motorola interrupts 39 non-disclosure agreement required 4.6 hardware interrupts all hardware interrupts except reset are maskable by the i bit in the ccr. if the i bit is set, all hardware interrupts (internal and external) are disabled. clearing the i bit enables the hardware interrupts. the two types of hardware interrupts are explained in the following sections. 4.7 external interrupt (irq) the irq pin provides an asynchronous interrupt to the cpu. a block diagram of the irq function is shown in figure 4-2 . note: the bih and bil instructions will apply only to the level on the irq pin itself, and not to the output of the logic or function with the port c irq interrupts. the state of the individual port c pins can be checked by reading the appropriate port c pins as inputs. figure 4-2. irq function block diagram the irq pin is one source of an external interrupt. all port c pins (pc0Cpc7) act as other external interrupt sources if the keyscan feature is enabled as specified by the user. when edge sensitivity is selected for the irq interrupt, it is sensitive to: ? falling edge on the irq pin ? falling edge on any port c pin with keyscan enabled irq latch r irq pin level (mask option) to irq processing in cpu port c to bih & bil instruction sensing rst irq vector fetch v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required interrupts general release specification MC68HC705CT4 rev. 2.0 40 interrupts motorola when edge and level sensitivity is selected for the irq interrupt, it is sensitive to the following cases: ? low level on the irq pin ? falling edge on the irq pin ? falling edge or low level on any port c pin with keyscan enabled 4.8 external interrupt timing if the interrupt mask bit (i bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts. the interrupt request is latched immediately following the falling edge of the irq source. the interrupt request is then synchronized internally and serviced as specified by the contents of $1ffa and $1ffb. either a level-sensitive and edge-sensitive trigger or an edge-sensitive- only trigger is available via the mask programmable option for the irq pin. 4.9 16-bit timer interrupt three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. the interrupt flags are in the timer status register (tsr), and the enable bits are in the timer control register (tcr). any of these interrupts vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1ff8 and $1ff9. 4.10 ssi interrupt two different synchronous serial interrupt (ssi) flags cause an ssi interrupt whenever they are set and enabled. the interrupt flags are in the ssi status register (sssr), and the enable bits are in the ssi control register (sscr). either of these interrupts vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1ff6 and $1ff7. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts core timer interrupt MC68HC705CT4 rev. 2.0 general release specification motorola interrupts 41 non-disclosure agreement required 4.11 core timer interrupt this timer can create two types of interrupts. a timer overflow interrupt occurs whenever the 8-bit timer rolls over from $ff to $00 and the enable bit tofe is set. a real-time interrupt occurs whenever the programmed time elapses and the enable bit rtie is set. either of these interrupts vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1ff4 and $1ff5. 4.12 comparator 3 interrupt comparator 3 can create an interrupt when its output (cmp3) gets set and the enable bit cm3ie is set. the interrupt service routine is located at the address specified by the contents of memory locations $1ffa and $1ffb. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required interrupts general release specification MC68HC705CT4 rev. 2.0 42 interrupts motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola resets 43 non-disclosure agreement required general release specification MC68HC705CT4 section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.3 external reset ( reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 power-on reset (por). . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2 computer operating properly reset (copr) . . . . . . . . . . .46 5.4.2.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2.2 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2.3 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2.4 cop watchdog timer considerations . . . . . . . . . . . . . . .47 5.4.2.5 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.4.3 illegal address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.2 introduction the mcu can be reset from four sources: one external input and three internal restart conditions. the reset pin is an input with a schmitt trigger as shown in figure 5-1 . all the internal peripheral modules will be reset by the internal reset signal (rst). refer to figure 5-2 for reset timing detail. 5.3 external reset ( reset) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active-low input will generate the rst signal and f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required resets general release specification MC68HC705CT4 rev. 2.0 44 resets motorola reset the cpu and peripherals. termination of the external reset input or the internal cop watchdog reset are the only reset sources that can alter the operating mode of the mcu. note: activation of the rst signal is generally referred to as reset of the device, unless otherwise specified. figure 5-1. reset block diagram cpu latch reset cop watchdog (copr) rst osc data address ph2 to other peripheral s s irq/v ts t mode select to irq logic latch r power-on reset (por) v dd illegal address (illaddr) address clocked d d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola resets 45 resets external reset (reset) non-disclosure agreement required pch pcl osc1 2 reset internal processor internal address bus 1 1ffe 1fff v dd 4064 t cyc t cyc t rl internal data bus 1 1ffe 1ffe 1ffe 1ffe new 1fff notes: 1. internal timing signal and bus information not available externally 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 4. v dd must fall to a level lower than v por to be recognized as a power-on reset. 3 new new op code pcl pch new new op code new clock 1 0 v > v por 4 figure 5-2. reset and por timing diagram pc pc pc pc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required resets general release specification MC68HC705CT4 rev. 2.0 46 resets motorola 5.4 internal resets the three internally generated resets are the initial power-on reset function, the cop watchdog timer reset, and the illegal address detector. termination of the external reset input or the internal cop watchdog timer are the only reset sources that can alter the operating mode of the mcu. the other internal resets do not have any effect on the mode of operation when their reset state ends. 5.4.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabilize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064 internal processor bus clock cycles (ph2) after the oscillator becomes active. the por generates the rst signal that resets the cpu. if any other reset function is active at the end of this 4064-cycle delay, the rst signal remains in the reset condition until the other reset condition(s) end. during the por, the reset pin is forced low. 5.4.2 computer operating properly reset (copr) the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to time out, an internal reset is generated to reset the mcu. regardless of an internal or external reset, the mcu comes out of a cop reset according to the standard rules of mode selection. the cop reset function is enabled or disabled by a mask option and is verified during production testing. 5.4.2.1 resetting the cop writing a zero to the copf bit prevents a cop reset. this action resets the counter and begins the timeout period again. the copf bit is bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets internal resets MC68HC705CT4 rev. 2.0 general release specification motorola resets 47 non-disclosure agreement required of address $1ff0. a read of address $1ff0 returns user data programmed at that location. 5.4.2.2 cop during wait mode the cop continues to operate normally during wait mode. the software should pull the device out of wait mode periodically and reset the cop by writing to the copf bit to prevent a cop reset. 5.4.2.3 cop during stop mode when the stop enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. when stop is executed, the cop counter will hold its current state. if a reset is used to exit stop mode, the cop counter is reset and held until 4064 por cycles are completed, at that time, counting will begin. if an external irq is used to exit stop mode, the cop counter does not wait for the completion of the 4064 por cycles but it does count these cycles. it is recommended, therefore, that the cop is fed before executing the stop instruction. 5.4.2.4 cop watchdog timer considerations the cop watchdog timer is active in all modes of operation if enabled by a mask option. if the cop watchdog timer is selected by a mask option, any execution of the stop instruction (either intentional or inadvertent due to the cpu being disturbed) causes the oscillator to halt and prevent the cop watchdog timer from timing out. if the cop watchdog timer is selected by a mask option, the cop resets the mcu when it times out. therefore, it is recommended that the cop watchdog is disabled for a system that must have intentional uses of the wait mode for periods longer than the cop timeout period. the recommended interactions and considerations for the cop watchdog timer, stop instruction, and wait instruction are summarized in table 5-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required resets general release specification MC68HC705CT4 rev. 2.0 48 resets motorola 5.4.2.5 cop register the cop register is shared with the msb of an unimplemented user interrupt vector as shown in figure 5-3 . reading this location returns whatever user data has been programmed at this location. writing a zero to the copr bit in this location clears the cop watchdog timer. 5.4.3 illegal address an illegal address reset is generated when the cpu attempts to fetch an instruction from either unimplemented address space ($0130 to $0aff) or i/o address space ($0000 to $002f). table 5-1. cop watchdog timer recommendations if the following conditions exist: then the cop watchdog timer should be: wait time wait time less than cop timeout enable or disable cop by mask option wait time more than cop timeout disable cop by mask option any length wait time disable cop by mask option addr register name bit 7 654321 bit 0 $1ff0 unimplemented vector and cop watchdog timer read: xxxxxxxx write: copr = unimplemented figure 5-3. cop watchdog timer location f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola operating modes 49 non-disclosure agreement required general release specification MC68HC705CT4 section 6. operating modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.3 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4 bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5.2 stop recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.5.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.5.4 low-power wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.2 introduction the mcu has two modes of operation: single-chip mode and bootloader mode with two oscillator options. table 6-1 shows the conditions required to go into each mode. table 6-1. operating mode conditions reset irq pb1 pd5 mode v tst = 2 x v dd v ss Cv dd v tst v ss Cv dd v dd v ss Cv dd v ss single-chip self-check f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required operating modes general release specification MC68HC705CT4 rev. 2.0 50 operating modes motorola 6.3 single-chip mode in single-chip mode, the address and data buses are not available externally, but there are three 8-bit input/output (i/o) ports and one 7-bit i/o port. this mode allows the mcu to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. all address and data activity occurs within the mcu. single- chip mode is entered on the rising edge of reset if the irq/v pp pin is within normal operating range. figure 6-1. single-chip mode pinout of the MC68HC705CT4 34 39 pc1 pc2 pc3 pc4 pc5 pc6 pc7/pwm osc2 osc1 pd3/cmp2C 29 pd2/cmp12+ 7 12 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pb3 pb4 17 pb5 pb6 18 23 28 640 1 reset irq /v pp pa4 pa5 pa7 v ss v dd pd6/tcmp pd5/sck pa6 pd1/cmp1C pd0/cmp3+ v ss2 finr pdoutr pb7 pdout v dd2 pd4/sdio pc0 tcap fint f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes bootloader mode MC68HC705CT4 rev. 2.0 general release specification motorola operating modes 51 non-disclosure agreement required 6.4 bootloader mode bootloader mode is entered upon the rising edge of reset if the irq is at v tst and the pb1 pin is at logic one. the bootloader code resides in the rom from $1f01 to $1fef. this program handles copying of user code from an external eprom into the on-chip eprom. the bootload function does not have to be done from an external eprom, but it may be done from a host. (see section 15. eprom .) 6.5 low-power modes the following paragraphs describe the low-power modes. 6.5.1 stop mode the stop instruction places the mcu in its lowest power-consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. during stop mode, the ctcsr ($08) bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. the timer prescaler is cleared. the i bit in the ccr is cleared to enable external interrupts. all other registers and memory remain unaltered. all input/output lines remain unchanged. the processor can be brought out of stop mode only by an external interrupt or reset. 6.5.2 stop recovery the processor can be brought out of the stop mode only by an external interrupt or reset. see figure 6-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required operating modes general release specification MC68HC705CT4 rev. 2.0 52 operating modes motorola 6.5.3 wait mode the wait instruction places the mcu in a low power-consumption mode, but the wait mode consumes more power than the stop mode. all cpu action is suspended, but the core timer, the oscillator, and any enabled module remain active. any interrupt or reset will cause the mcu to exit the wait mode. the user must shut off subsystems to reduce power consumption. wait current specifications assume cpu operation only and do not include current consumption by any other subsystems. figure 6-2. stop recovery timing diagram 1ffe 1ffe 1ffe 1ffe 1fff internal address bus internal clock irq/v pp 3 irq/v pp 2 reset osc1 1 t ilch 4064 t cyc reset or interrupt vector fetch t lih t rl notes: 1. represents the internal gating of the osc1 pin 2. irq/v pp pin edge-sensitive mask option 3. irq/v pp pin level- and edge-sensitive mask option f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes low-power modes MC68HC705CT4 rev. 2.0 general release specification motorola operating modes 53 non-disclosure agreement required during wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and input/output lines remain in their previous state. the timer may be enabled to allow a periodic exit from wait mode. 6.5.4 low-power wait when the wait mode is entered by executing the wait instruction, the oscillator divider changes from a divide-by-5 to a divide-by-40 (additional divide-by-8) to lower the wait current. as a result, this gives a cpu clock rate of 256 khz if the oscillator is running with a 10.24-mhz crystal. the oscillator divide-by-5 or divide-by-40 option is also controlled by the speed bit located in the miscellaneous control register ($21). section 14. miscellaneous register . when returning from wait mode via an interrupt, the osc rate prior to entering wait mode is restored. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required operating modes general release specification MC68HC705CT4 rev. 2.0 54 operating modes motorola figure 6-3. stop/wait flowchart y stop oscillator active timer clock active processor clocks stopped clear i bit (irq) external reset reset turn on oscillator wait for time delay to stabilize 1. fetch reset vector or 2 service interrupt a. stack b. set i bit c. vector to interrupt routine restart processor clock wait stop oscillator and all clocks clear i bit interrupt timer interrupt (irq) external 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine y y y y n n n n n interrupt ssi y n interrupts core timer n interrupt y f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola parallel input/output (i/o) 55 non-disclosure agreement required general release specification MC68HC705CT4 section 7. parallel input/output (i/o) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.7 input/output port pin programming . . . . . . . . . . . . . . . . . . . . .57 7.2 introduction in user mode 31 lines are arranged as one 7-bit and three 8-bit ports. most of these port pins are programmable as either inputs or outputs under software control of the data direction registers, though some are input only. note: to avoid a glitch on the output pins, write data to the i/o port data register before writing a logic 1 to the corresponding data direction register. 7.3 port a port a is an 8-bit bidirectional port that does not share any of its pins with other subsystems. the port a data register is at $0000 and the data direction register (ddr) is at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a logic 1 to a ddr bit sets the corresponding port bit to output mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required parallel input/output (i/o) general release specification MC68HC705CT4 rev. 2.0 56 parallel input/output (i/o) motorola 7.4 port b port b is an 8-bit bidirectional port. the port b data register is at $0001 and the data direction register (ddr) is at $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a logic 1 to a ddr bit sets the corresponding port bit to output mode. 7.5 port c port c is an 8-bit bidirectional port. the port c data register is at $0002 and the data direction register (ddr) is at $0006. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a logic 1 to a ddr bit sets the corresponding port pin to output mode. each of the port c pins has an optional pullup device. when the ddr bit is cleared and the pullup device is enabled, the pin will be a pullup and an interrupt pin. the edge- or edge- and level-sensitivity of the irq pin also pertains to the enabled port c pins. care needs to be taken when using port c pins that have the pullup enabled. before switching from an output to an input, the data should be preconditioned to a logic 1 to prevent an interrupt from occurring. port c bit 7 is also shared with the pwm output. when pc7 is used as the pwm output, its pullup option should not be selected (see figure 7-1 ). figure 7-1. port c pullup option pc7 v dd v dd ddr bit normal port circuitry as shown in figure 7-2 irq schmitt trigger to interrupt logic mask option (pc7pu) disabled enabled (pc7 adds pwm) from all other port c pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port d MC68HC705CT4 rev. 2.0 general release specification motorola parallel input/output (i/o) 57 non-disclosure agreement required 7.6 port d port d is a 7-bit bidirectional port. two of its pins are shared with the ssi subsystem, four are shared with the comparators, and one is shared with the timer. during reset, all seven bits become valid input ports because all special function output drivers associated with the timer and ssi subsystems are disabled. 7.7 input/output port pin programming port pins may be programmed as inputs or outputs under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each i/o port has an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set to a logic one. a pin is configured as an input if its corresponding ddr bit is cleared to a logic 0. at power-on or reset, all ddrs are cleared, which configures all pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. refer to table 7-1 and to figure 7-2 for additional information. table 7-1. i/o pin functions r/ w ddr i/o pin functions 00 the i/o pin is in input mode. data is written into the output data latch. 01 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 11 the i/o pin is in an output mode. the output data latch is read. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required parallel input/output (i/o) general release specification MC68HC705CT4 rev. 2.0 58 parallel input/output (i/o) motorola figure 7-2. i/o circuitry latched output data bit i/o input reg bit input i/o output data direction register bit internal hc05 connections pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola 16-bit timer 59 non-disclosure agreement required general release specification MC68HC705CT4 section 8. 16-bit timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.3 counter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 8.4 output compare register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 8.5 input capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 8.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.8 timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 8.9 timer during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 8.10 timer power supply source . . . . . . . . . . . . . . . . . . . . . . . . . . .67 8.2 introduction the timer consists of a 16-bit, free-running counter driven by a fixed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements, while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. these registers contain the high and low byte of that functional segment. access of the high byte inhibits that specific timer function until the low byte is also accessed. note: the i bit in the ccr should be set while manipulating both the high and low byte registers of a specific timer function to ensure that an interrupt does not occur. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required 16-bit timer general release specification MC68HC705CT4 rev. 2.0 60 16-bit timer motorola 8.3 counter register the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18C$19 (counter register) or $1aC$1b (counter alternate register). if a read of the free-running counter or counter alternate register is from the least significant byte (lsb) ($19, $1b), the lsb receives the count value at the time of the read. if a read of the free- running counter or counter alternate register first addresses the most significant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains fixed after the first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb also must be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 16-bit timer counter register MC68HC705CT4 rev. 2.0 general release specification motorola 16-bit timer 61 non-disclosure agreement required figure 8-1. 16-bit timer block diagram the free-running counter is configured to $fffc during reset and is a read-only register but only when the timer is enabled. during a power-on reset, the counter is also preset to $fffc and begins running only after the ton bit in the timer control register is set. because the free- running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. when the counter rolls over from $ffff to $0000, the tof bit is set. an interrupt can also be enabled when counter roll-over occurs by setting its interrupt enable bit (toie). note: the i bit in the ccr should be set while manipulating both the high and low byte registers of a specific timer function to ensure that an interrupt does not occur. input capture register clock internal bus output compare register high byte low byte $16 $17 ? ? ? ? ? 4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $1a $1b $18 $19 high byte low byte $14 $15 output compare circuit overflow detect circuit edge detect circuit timer status reg. icf ocf tof $13 icie iedg olvl output level reg. reset timer control reg. $12 output level (tcmp) interrupt circuit toie ocie edge input (tcap) d clk c q folvl pd6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required 16-bit timer general release specification MC68HC705CT4 rev. 2.0 62 16-bit timer motorola 8.4 output compare register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. the output compare register contents are continually compared with the contents of the free-running counter. if a match is found, the corresponding output compare flag (ocf) bit is set and the corresponding output level (olvl) bit is clocked to an output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare flag (ocf) is set or clear. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 16-bit timer input capture register MC68HC705CT4 rev. 2.0 general release specification motorola 16-bit timer 63 non-disclosure agreement required 8.5 input capture register two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the level transition that triggers the counter transfer is defined by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained by an input capture is one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register msb ($14), the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required 16-bit timer general release specification MC68HC705CT4 rev. 2.0 64 16-bit timer motorola 8.6 timer control register the tcr is a read/write register containing six control bits. three bits control interrupts associated with the timer status register flags icf, ocf, and tof. icie input capture interrupt enable 1 = interrupt enabled 0 = interrupt disabled ocie output compare interrupt enable 1 = interrupt enabled 0 = interrupt disabled toie timer overflow interrupt enable 1 = interrupt enabled 0 = interrupt disabled ton timer on when disabled, the timer is initialized to the reset condition. 1 = timer enabled 0 = timer disabled iedg input edge value of input edge determines which level transition on the tcap pin will trigger a free-running counter transfer to the input capture register. reset clears this bit. 1 = positive edge 0 = negative edge address: $0012 bit 7 654321 bit 0 read: icie ocie toie 0 0 ton iedg olvl write: reset: 00000000 figure 8-2. timer control register (tcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 16-bit timer timer status register MC68HC705CT4 rev. 2.0 general release specification motorola 16-bit timer 65 non-disclosure agreement required olvl output level value of output level is clocked into the output level register by the next successful output compare and will appear on the tcmp pin. 1 = high output 0 = low output 8.7 timer status register the tsr is a read-only register containing three status flag bits. icf input capture flag 1 = flag set when selected polarity edge is sensed by input capture edge detector 0 = flag cleared when tsr and input capture low register ($15) are accessed reset clears this bit. ocf output compare flag 1 = flag set when output compare register contents match the free- running counter contents 0 = flag cleared when tsr and output compare low register ($17) are accessed reset clears this bit. address: $0013 bit 7 654321 bit 0 read: icf ocf tof 00000 write: reset: 00000000 = unimplemented figure 8-3. timer status register (tsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required 16-bit timer general release specification MC68HC705CT4 rev. 2.0 66 16-bit timer motorola tof timer overflow flag 1 = flag set when free-running counter transition from $ffff to $0000 occurs 0 = flag cleared when tsr and counter low register ($19) are accessed reset clears this bit. bits 0C4 not used always read zero. accessing the timer status register satisfies the first condition required to clear status bits. the remaining step is to access the register corresponding to the status bit. a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: ? the timer status register is read or written when tof is set. ? the msb of the free-running counter is read but not for the purpose of servicing the flag. the counter alternate register at address $1a and $1b contains the same value as the free-running counter at address $18 and $19; this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 8.8 timer during wait mode the cpu clock halts during wait mode, but the timer remains active if turned on prior to entering wait mode. if interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 16-bit timer timer during stop mode MC68HC705CT4 rev. 2.0 general release specification motorola 16-bit timer 67 non-disclosure agreement required 8.9 timer during stop mode in stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. if reset is used, the counter is forced to $fffc. during stop, if the timer is on and at least one valid input capture edge occurs at the tcap pin, the input capture detect circuit is armed. this does not set any timer flags or wake up the mcu. when the mcu does wake up, however, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. if reset is used to exit stop mode, no input capture flag or data remains, even if a valid input capture edge occurred. 8.10 timer power supply source the timers power is supplied by v dd and v ss . v dd2 and v ss2 will not be needed since this module is not susceptible to supply noise. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required 16-bit timer general release specification MC68HC705CT4 rev. 2.0 68 16-bit timer motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola synchronous serial interface (ssi) 69 non-disclosure agreement required general release specification MC68HC705CT4 section 9. synchronous serial interface (ssi) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.3 signal format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.3.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.3.2 serial data in/out (sdio) . . . . . . . . . . . . . . . . . . . . . . . . . .71 9.4 ssi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.4.1 ssi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.4.2 ssi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 9.4.3 ssi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 9.5 operation during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 9.6 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 9.7 ssi power supply source . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 9.2 introduction the synchronous serial interface (ssi) is a 2-wire master/slave system including serial clock (sck) and serial data input/output (sdio). data is transferred eight bits at a time. a software programmable option determines whether the ssi transfers data most significant bit (msb) or least significant bit (lsb) first and an interrupt may be generated at the completion of each transfer. when operating as a master device, the serial clock speed is selectable from a choice of four rates. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705CT4 rev. 2.0 70 synchronous serial interface (ssi) motorola transmission in master mode is initiated by a write to the ssi data register (sdr). a transfer cannot be initiated in slave mode; the external master initiates the transfer. the programmer must choose between master or slave mode before the ssi is enabled. the programmer must ensure that only one master exists in the system at any one time. all devices in the system must operate with the same clock polarity and data rates. slaves should always be disabled before the master is disabled. figure 9-1. ssi block diagram interrupt circuit to interrupt logic ssi status reg. ssi control reg. ssi data reg. hff sdio sck clock generator sf dcol start se mstr sr lsbf control logic 000000 se data bus controls/address bus interrupt mcu internal bus cpol mstr t/r & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) signal format MC68HC705CT4 rev. 2.0 general release specification motorola synchronous serial interface (ssi) 71 non-disclosure agreement required 9.3 signal format the ssi is comprised of two main input/output (i/o) signals that interface with port d serial clock and serial data. 9.3.1 serial clock (sck) when se = 0, this pin is a port d bit 5 pin, which follows the port d ddr assignment. in master mode (mstr = 1), the serial clock (sck) pin is an output with four selectable frequencies. this pin will be high (cpol = 1) or low (cpol = 0) between transmissions. in slave mode (mstr = 0), the sck pin is an input and the clock must be supplied by an external master with a maximum frequency of f op /2. there is no minimum sck frequency. this pin should be driven high (cpol = 1) or low (cpol = 0) between transmissions by the external master and must be stable before the ssi is first enabled (se = 1). data is always captured at the serial data in/out (sdio) pin on the rising edge of sck. data is always shifted out and presented at the serial data in/out (sdio) pin on the falling edge of sck. 9.3.2 serial data in/out (sdio) prior to enabling the ssi (se = 0), the serial data in/out (sdio) pin is a port d bit 4 pin, which follows the port d ddr assignment. when the ssi is enabled (se = 1) the sdio pin becomes a high-impedance input pin if the t/ r bit is low or it idles high if the t/ r bit is high. the data can be sent or received in either msb first format (lsbf = 0) or lsb first format (lsbf = 1). if (cpol = 1), the first falling edge of sck will shift the first data bit out to the sdio pin. subsequent falling edges of sck will shift the remaining data bits out. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705CT4 rev. 2.0 72 synchronous serial interface (ssi) motorola if (cpol = 0), the first data bit will be driven out to the sdio pin before the first rising edge of sck. subsequent falling edges of sck will shift the remaining data bits out. when receiving data in master mode, the t/ r bit must be low and data must be written to the data register to initiate clock generation. when transmitting data in master mode, the t/ r bit must be high. when receiving data in slave mode, t/ r bit must be low and the clock and data must be supplied by external device. when transmitting data in slave mode, t/ r bit must be high, and data must be written to the data register before the ssi is enabled to ensure that proper data is transferred. figure 9-2. serial i/o port timing 9.4 ssi registers the ssi has three registers: control, status, and data. 9.4.1 ssi control register this register is located at address $001e and contains seven bits. a reset clears all of these bits, except bit 3 which is set. writes to this register during a transfer should be avoided, with the exception of clearing the se bit to disable the ssi. in addition, the clock polarity, rate, data format and master/slave selection should not be changed while the ssi is enabled (se = 1) or sdio bit 1 bit 2 bit 3 bit 7 sck bit 8 se sck (cpol = 1) (cpol = 0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) ssi registers MC68HC705CT4 rev. 2.0 general release specification motorola synchronous serial interface (ssi) 73 non-disclosure agreement required being enabled. always disable the ssi first, by clearing the se bit, before altering these control bits within the ssi control register (scr). sie ssi interrupt enable this bit determines whether an interrupt request should be generated when a transfer is complete. when set, an interrupt request is made if the cpu is in the run or wait mode of operation and status flag bit sf is set. when cleared, no interrupt requests are made by the ssi. se ssi enable when set, this bit enables the ssi, makes pd5 the sck pin, and makes pd4 the sdio pin. when se is cleared, any transmission in progress is aborted, the bit counter is reset, and pins sck and sdio revert to being pd5 and pd4. lsbf least significant bit (lsb)first when set, data is sent and received in a least significant bit (lsb) first format. when cleared, data is sent and received in a most significant bit (msb) first format. mstr master mode when set, this bit configures the ssi to the master mode. this means that the transmission is initiated by a write to the data register and the sck pin becomes an output providing a synchronous data clock at a rate determined by the sr bits. address: $001e bit 7 654321 bit 0 read: sie se lsbf mstr cpol t/ r sr1 sr0 write: reset: 00001000 figure 9-3. ssi control register (scr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705CT4 rev. 2.0 74 synchronous serial interface (ssi) motorola when cleared, this bit configures the ssi to the slave mode and aborts any transmission in progress. transfers are initiated by an external master, which should supply the clock to the sck pin. cpol clock polarity the clock polarity bit controls the state of the sck pin between transmissions. when this bit is set, pin sck is high between transmissions. when this bit is cleared, pin sck is low between transmissions. in both cases the data is latched on the rising edge of sck for serial input and is valid on the rising edge of sck for serial output. a reset sets this bit. note: if the ssi is used as a slave, the sck input pin must be active before enabling the ssi. for example, if cpol = 0, sck must be low; if cpol = 1, sck must be high. t/ r transmit/receive this bit must be set to allow data to be driven on the sdio pin (transmitting). it must be cleared to disable the sdio drivers when receiving data. it is cleared by a reset. sr1 and sr0 ssi rate these bits determine the frequency of sck when in master mode (mstr = 1). they have no effect in slave mode (mstr = 0). table 9-1. ssi rates sr1 and sr0 sck rates (hz) at f osc frequency 00 32 khz 01 64 khz 10 128 khz 11 256 khz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) ssi registers MC68HC705CT4 rev. 2.0 general release specification motorola synchronous serial interface (ssi) 75 non-disclosure agreement required 9.4.2 ssi status register this register is located at address $001c and contains two bits. reset clears both of these bits. sf ssi flag this bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken place. if mstr = 0 and sie = 0, this bit has no effect on any further transmissions and can be ignored without problem. however, the sf flag must be clear to write the data register, or if sie = 1 to clear the interrupt 1 = . if mstr = 1, the sf flag must be cleared between transfers. the sf flag can be cleared three different ways: (1) by reading the ssr with sf set, followed by a read or write of the serial data register, (2) by a system reset, or, (3) by disabling the ssi. if the sf flag is cleared before the last edge of the next byte, it will be set again. dcol data collision this is a read-only status bit, which indicates that an invalid access to the data register was made. an invalid access can be one of the following conditions: ? an access of the sdr register in the middle of a transfer (after the first falling edge of sck and before sf is set) ? an access of the sdr register made before an access of the ssr register (after sf is set) dcol is cleared by reading the status register with sf set followed by a read or write of the data register. a reset also clears this bit. address: $001c bit 7 654321 bit 0 read: sf dcol 000000 write: reset: 00000000 figure 9-4. ssi status register (ssr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705CT4 rev. 2.0 76 synchronous serial interface (ssi) motorola 9.4.3 ssi data register this register is located at address $001d and is both the transmit and receive data register. this system is not double buffered, but any writes to this register during transfers are masked and will not destroy the previous contents. the sdr can be read at any time, but, if a transfer is in progress the results may be ambiguous. the contents of this register could be altered whenever the cpol bit is altered. this register should be written to only upon completion of a transfer, after the sf flag has been cleared. otherwise, the new data will not be stored. for an ssi configured as a master, to initiate a transfer, the data register write must occur after the ssi is enabled. 9.5 operation during wait mode the cpu clock halts during wait mode, but the ssi remains active. if interrupts are enabled, an ssi interrupt will cause the processor to exit wait mode. 9.6 operation during stop mode in stop mode, the ssi halts operation. the sdio and sck pins will maintain their states. if the ssi is nearing completion of a transfer when the stop mode is entered, it might be possible for the ssi to generate an interrupt request and thus cause the processor immediately to exit stop mode. to prevent address: $001d bit 7 654321 bit 0 read: write: reset: uuuuuuuu figure 9-5. ssi data register (sdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) ssi power supply source MC68HC705CT4 rev. 2.0 general release specification motorola synchronous serial interface (ssi) 77 non-disclosure agreement required this occurrence, the programmer should ensure that all transfers are complete before entering the stop mode. if the ssi is configured to slave mode, further care should be taken in entering stop mode. the sck pin will still accept a clock from an external master, allowing potentially unwanted transfers to take place and power consumption to be increased. the ssi will not generate interrupt requests in this situation but, on exiting stop mode through some other means, the sf flag may be found to be set and an interrupt request will be generated if sie is also set at this point. to avoid these potential problems, it is safer to disable the ssi completely (se = 0) before entering stop mode. the synchronous serial interface (ssi) is a 2-wire master/slave system including serial clock (sck) and serial data input/output (sdio). when operating as a master device, the serial clock speed is selectable between four rates. 9.7 ssi power supply source the power supplied to the ssi is v dd and v ss , thus keeping the v dd2 and v ss2 free for the noise susceptible modules. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705CT4 rev. 2.0 78 synchronous serial interface (ssi) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola core timer 79 non-disclosure agreement required general release specification MC68HC705CT4 section 10. core timer 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 10.3 core timer control and status register. . . . . . . . . . . . . . . . . .81 10.4 core timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . .83 10.5 computer operating properly (cop) reset . . . . . . . . . . . . . . .84 10.6 timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 10.7 core timer power supply source . . . . . . . . . . . . . . . . . . . . . .84 10.2 introduction the core timer for this device is a 12-stage multifunctional ripple counter. features include timer overflow, power-on reset (por), real-time interrupt (rti), and cop watchdog timer. as seen in figure 10-1 , the internal peripheral clock is divided by four, and then drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the core timer counter register (ctcr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt rate of the internal peripheral clock(e)/1024. this point is then followed by three more stages, with the resulting clock (e/16384) driving the real- time interrupt circuit (rti). the rti circuit consists of three divider stages with a one-of-four selector. the output of the rti circuit is further divided by eight to drive the mask optional cop watchdog timer circuit. the rti rate selector bits and the rti and ctof enable bits and flags are located in the timer control and status register at location $08. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required core timer general release specification MC68HC705CT4 rev. 2.0 80 core timer motorola figure 10-1. core timer block diagram cop clear internal bus $09 core timer counter register (ctcr) 5-bit counter ctof rtif tofe rtie rt1 interrupt circuit $08 rti select circuit status register rt0 timer control & overflow circuit detect cop watchdog timer (? ? 8) to reset logic 8 8 rtfc tofc e/2 10 tcbp ctcsr ctcr internal peripheral clock (e) to interrupt logic rtiout e / 2 12 por e/2 2 div ? 4 e / 2 17 e / 2 16 e / 2 15 e / 2 14 2 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core timer core timer control and status register MC68HC705CT4 rev. 2.0 general release specification motorola core timer 81 non-disclosure agreement required 10.3 core timer control and status register the ctcsr contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. figure 10-2 shows the value of each bit in the ctcsr when coming out of reset. ctof core timer overflow ctof is a read-only status bit set when the 8-bit ripple counter rolls over from $ff to $00. clearing ctof is done by writing a logic 1 to tofc. writing to ctof has no effect. reset clears ctof. rtif real time interrupt flag the real-time interrupt circuit consists of a 3-stage divider and a one- of-four selector. the clock frequency that drives the rti circuit is e/2**14 (or e/16,384) with three additional divider stages, giving a maximum interrupt period of 64 milliseconds at a bus rate of 2.048 mhz. rtif is a clearable, read-only status bit and is set when the output of the chosen (one-of-four selection) stage goes active. clearing rtif is done by writing a logic 1 to rtfc. writing to rtif has no effect. reset clears rtif. tofe timer overflow enable when this bit is set, a cpu interrupt request is generated when the ctof bit is set. reset clears this bit. rtie real-time interrupt enable when this bit is set, a cpu interrupt request is generated when the rtif bit is set. reset clears this bit. address $0008 bit 7 654321 bit 0 read: ctof rtif tofe rtie 00 rt1 rt0 write: tofc rtrc reset: 00000011 = unimplemented figure 10-2. core timer control and status register (ctcsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required core timer general release specification MC68HC705CT4 rev. 2.0 82 core timer motorola tofc timer overflow flag clear when a logic 1 is written to this bit, ctof is cleared. writing a logic 0 has no effect on the ctof bit. this bit always reads as zero. rtfc real-time interrupt flag clear when a logic 1 is written to this bit, rtif is cleared. writing a logic 0 has no effect on the rtif bit. this bit always reads as zero. rt1 and rt0 real-time interrupt rate select these two bits select one of four taps from the real-time interrupt circuit. see table 10-2 . reset sets these two bits, which selects the slowest periodic rate and gives the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the timeout period is imminent or uncertain. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing rti taps. table 10-1. table 10-2rti and cop rates at 2.048 mhz rti rate 2.048 mhz rt1 and rt0 minimum cop rates 2.048 mhz 8 ms 2 14 /e 00 (2 17 C2 14 )/e 56 ms 16 ms 2 15 /e 01 (2 18 C2 15 )/e 112 ms 32 ms 2 16 /e 10 (2 19 C2 16 )/e 224 ms 64 ms 2 17 /e 11 (2 20 C2 17 )/e 448 ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core timer core timer counter register MC68HC705CT4 rev. 2.0 general release specification motorola core timer 83 non-disclosure agreement required 10.4 core timer counter register the timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked by the cpu clock (e/4) and can be used for various functions including a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location, thereby simulating a 16-bit (or more) counter. the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer starts counting up from zero and normal device operation begins. when reset is asserted any time during operation (other than por), the counter chain is cleared. address $0009 bit 7 654321 bit 0 read: d7 d6 d5 d4 d3 d2 d1 d0 write: reset: 00000011 = unimplemented figure 10-3. core counter register (ctcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required core timer general release specification MC68HC705CT4 rev. 2.0 84 core timer motorola 10.5 computer operating properly (cop) reset the cop watchdog timer function is implemented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 10-2 . if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. preventing a cop timeout or clearing the cop is accomplished by writing a logic 0 to bit 0 of address $1ff0. when the cop is cleared, only the final divide-by-eight stage (output of the rti) is cleared. if the cop watchdog timer is allowed to time out, an internal reset is generated to reset the mcu. in addition, the reset pin is pulled low for a minimum of one e-clock cycle for emulation purposes. the cop remains enabled after execution of the wait instruction and all associated operations apply. if the stop instruction is disabled, execution of stop instruction causes the cpu to execute a nop instruction. in addition, the cop is prohibited from being held in reset. this prevents a device lock-up condition. this cops objective is to make it impossible for this device to become stuck or locked-up and to be sure the cop is able to rescue the part from any situation where it might entrap itself in abnormal or unintended behavior. this function is a mask option. 10.6 timer during wait mode the cpu clock halts during wait mode, but the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. the cop is always enabled while in user mode. 10.7 core timer power supply source the core timer is supplied by v dd and v ss . v dd2 and v ss2 are not needed here because this module is not susceptible to supply noise. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola dual phase-locked loop (pll) 85 non-disclosure agreement required general release specification MC68HC705CT4 section 11. dual phase-locked loop (pll) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.3.1 dual control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.3.2 12-bit reference counter modulus register. . . . . . . . . . . .89 11.3.3 16-bit transmit counter modulus register . . . . . . . . . . . . .90 11.3.4 16-bit receive counter modulus register . . . . . . . . . . . . .91 11.4 pll power supply source . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required dual phase-locked loop (pll) general release specification MC68HC705CT4 rev. 2.0 86 dual phase-locked loop (pll) motorola 11.2 introduction this dual pll is similar to that of the mc145162 60-mhz universal programmable dual pll frequency synthesizer. it is especially designed for ct-1 cordless phone applications. the pll features fully programmable 16-bit receive, 16-bit transmit, and 12-bit reference ripple down counters. it also has two independent phase detectors for transmit and receive loops. the fintx and finrx signals are input to the pll transmit and receive counters, respectively. they are typically driven by the loop vco and ac-coupled. the minimum input signal level is 200 mv p-p @ 60.0 mhz. figure 11-1. dual pll block diagram osc 12-bit programmable reference counter ? 4 ? 5 txpdout rxpdout 16-bit programmable tx counter 16-bit programmable rx counter fint finr pls1 pls0 mcu bus (10.24 mhz) ? 25 tx phase detector rx phase detector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dual phase-locked loop (pll) registers MC68HC705CT4 rev. 2.0 general release specification motorola dual phase-locked loop (pll) 87 non-disclosure agreement required 11.3 registers the pll has one 12-bit programmable counter, two 16-bit programmable counters, and one control register. 11.3.1 dual control register the pllcr contains bits that affect the operation of the pll. pls1 and pls0 pll reference counter select these bits select between the pll reference counter mux outputs. this output signal then drives the phase detectors. rxon rx counter enable when set, this bit enables the pll receive counter. when clear, it stops the receive counter in a reset state to save power. rxon also shuts off the associated phase detector and holds it in three-state. initializing the receive counter before it is enabled is recommended. address: $000a bit 7 654321 bit 0 read: tlock rlock refon txon rxon pls1 pls0 write: reset: 00000000 = unimplemented figure 11-2. dual pll control register table 11-1. pll reference counter select pls1 and pls0 pll reference counter output 00 ?? 12-bit counter 01 ?? ?4 after 12-bit counter 10 ?? 5 after 12-bit counter 11 ?? 25 after 12-bit counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required dual phase-locked loop (pll) general release specification MC68HC705CT4 rev. 2.0 88 dual phase-locked loop (pll) motorola txon tx counter enable when set, this bit enables the pll transmit counter. when clear, it stops the counter in a reset state to save power. txon also shuts off the associated phase detector and holds it in three- state. initializing the transmit counter before it is enabled is recommended. refon reference counter enable when set, this bit enables the pll reference counter. when clear, refon stops the reference counter in a reset state to save power. initializing the reference counter before it is enabled is recommended. rlock receive lock detect this bit is read only and is not latched. when set, this bit is a real-time indication of an active correction pulse from the phase detect in progress. when clear, no correction is made and the output from the phase detect is three-stated. using multiple reads at known intervals will allow the user to filter and judge a lock condition. tlock transmit lock detect this bit is read only and is not latched.when set, this bit is a real-time indication of an active correction pulse from the phase detect in progress. when clear, no correction is made and the output from the phase detect is three-stated. using multiple reads at known intervals will allow the user to filter and judge a lock condition. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dual phase-locked loop (pll) registers MC68HC705CT4 rev. 2.0 general release specification motorola dual phase-locked loop (pll) 89 non-disclosure agreement required 11.3.2 12-bit reference counter modulus register this 2-byte register holds the count for the 12-bit reference counter. the reference counter is shut off and held in reset when the refon bit is cleared. for proper operation, this register must not be loaded with a value less than $000f. note: bit 4 to bit 7 of $000b are not used but they are physically present. the user may use these four bits for scratch memory. address: $000b bit 7 654321 bit 0 read: pllrc11 pllrc10 pllrc9 pllrc8 write: reset: 00000000 address: $000c bit 7 654321 bit 0 read: pllrc7 pllrc6 pllrc5 pllrc4 pllrc3 pllrc2 pllrc1 pllrc0 write: reset: 00000000 = unimplemented figure 11-3. 12-bit reference counter (pllrc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required dual phase-locked loop (pll) general release specification MC68HC705CT4 rev. 2.0 90 dual phase-locked loop (pll) motorola 11.3.3 16-bit transmit counter modulus register this 2-byte register holds the count for the 16-bit transmit counter. the transmit counter is shut off and held in reset when the txon bit is cleared. for proper operation, this register must not be loaded with a value less than $000f. address: $000d bit 7 654321 bit 0 read: plltx15 plltx14 plltx13 plltx12 plltx11 plltx10 plltx9 plltx8 write: reset: 00000000 address: $000e bit 7 654321 bit 0 read: plltx7 plltx6 plltx5 plltx4 plltx3 plltx2 plltx1 plltx0 write: reset: 00000000 figure 11-4. 16-bit transmit counter (plltx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dual phase-locked loop (pll) registers MC68HC705CT4 rev. 2.0 general release specification motorola dual phase-locked loop (pll) 91 non-disclosure agreement required 11.3.4 16-bit receive counter modulus register this 2-byte register holds the count for the 16-bit receive counter. the receive counter is shut off and held in reset when the rxon bit is cleared. for proper operation, this register must not be loaded with a value less than $000f. the modulus registers mentioned above have specific read/write logic. when the user updates the contents of the modulus registers, the msb must be written first and is temporarily stored in a temporary buffer. this inhibits the transfer of data from this level to the next level, which is the modulus register. when the lsb is written, all 12 or 16 bits (data from the temporary buffer and the mcu internal bus) are transferred to the modulus register simultaneously. this prevents the loading of bad data from the modulus register. a read of the data registers is the reverse of a write operation. a read of the lsb buffers the msb. a subsequent read of the msb reflects this buffered value. since only one temporary buffer exists, two sequential msb writes of different registers will result in only the last data value stored in the temporary buffer. the first value will be lost. address: $000f bit 7 654321 bit 0 read: pllrx15 pllrx14 pllrx13 pllrx12 pllrx11 pllrx10 pllrx9 pllrx8 write: reset: 00000000 address: $0010 bit 7 654321 bit 0 read: pllrx7 pllrx6 pllrx5 pllrx4 pllrx3 pllrx2 pllrx1 pllrx0 write: reset: 00000000 figure 11-5. 16-bit receive counter (pllrx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required dual phase-locked loop (pll) general release specification MC68HC705CT4 rev. 2.0 92 dual phase-locked loop (pll) motorola figure 11-6. counter structure block diagram 11.4 pll power supply source the pll is supplied by v dd , v dd2 , v ss , and v ss2 . v dd and v ss are reserved for the digital circuitry, while v dd2 and v ss2 are reserved for the analog circuitry such as the phase detect and the amplifiers which are sensitive to supply noise. mcu internal bus msb lsb modulus counter note: not available for the 12-bit reference counter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola pulse width modulator (pwm) 93 non-disclosure agreement required general release specification MC68HC705CT4 section 12. pulse width modulator (pwm) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12.4 pwm data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.5 pwm during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12.6 pwm during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12.7 pwm during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12.8 pwm power supply source . . . . . . . . . . . . . . . . . . . . . . . . . . .97 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required pulse width modulator (pwm) general release specification MC68HC705CT4 rev. 2.0 94 pulse width modulator (pwm) motorola 12.2 introduction the pulse width modulator (pwm) system has one 6-bit channel to enable the correct pulse output. the pwm has a fixed frequency of e/64, where e is the internal bus frequency. for a pwm output frequency of 32 khz, e must be 2.048 mhz. this corresponds to a 10.24-mhz crystal with the divide-by-five crystal option. figure 12-1. pwm block diagram buffer modulus & comparator 6-bit counter pwm pin logic pc7/pwm e miscellaneous control register hc05 data bus pwme f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator (pwm) functional description MC68HC705CT4 rev. 2.0 general release specification motorola pulse width modulator (pwm) 95 non-disclosure agreement required 12.3 functional description a $00 in the pwm data register yields an off output (0%), but a $3f yields a duty of 63/64 (98.4%). when not in use, the pwm system can be shut off to save power by clearing the pwme bit in miscr. writes to the pwm data register can be performed at any time without affecting the current pwm output signal. updates on the pwm output occur at the end of the pwm period (e x 64). at this time, the new value is loaded into the pwm data register. if a write to the registers is performed while the pwm is disabled, data is transferred directly to the pwm register. a read of the data register reads the active count in progress, not the buffered value. after the pwm is enabled (pwm = 1) the pwm output remains low for one e cycle. this allows synchronization and will not occur again until the next time the pwm is enabled. figure 12-2. pwm waveforms 10 3f 20 64 x e 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required pulse width modulator (pwm) general release specification MC68HC705CT4 rev. 2.0 96 pulse width modulator (pwm) motorola 12.4 pwm data register one pwm data register (pwmdr), located at $0020, is associated with the pwm system. this 8-bit data register holds the duty cycle for the pwm output; however, only six of these bits are used. pwmdr can be written to and read at any time. writes to the pwmdr are buffered and are not transferred to the active register until the end of the pwm cycle during which the write was executed. upon reset the user should write to the data register prior to enabling the pwm system (for example, prior to setting the pwme bit in the miscellaneous control register). this avoids an erroneous duty cycle from being driven. pwme miscellaneous control register pwm enable bit when set, this bit enables the pwm subsystem. its main function is to allow the user to save power when not using the pwm. when enabled, the clocks are active to the module. when clear, this bit shuts off the clocks to the module and relinquishes control of pc7 to the port c logic (the pc7 pullup option should not be selected if the pwm is used). reset clears this bit. this bit is located in the miscellaneous control register found in section 13. comparators . address: $0020 bit 7 654321 bit 0 read: 00 write: reset: unaffected by reset figure 12-3. pwm data register (pwmdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator (pwm) pwm during wait mode MC68HC705CT4 rev. 2.0 general release specification motorola pulse width modulator (pwm) 97 non-disclosure agreement required 12.5 pwm during wait mode the pwm continues normal operation during wait mode. to decrease power consumption during wait, it is recommended that the pwme bit in the miscellaneous control register be cleared if the pwm d/a converter is not being used. 12.6 pwm during stop mode in stop mode, the oscillator is stopped, causing the pwm to cease function. any signal in process is halted in whatever phase the signal happens to be in. disabling the pwm before executing the stop instruction is recommended. 12.7 pwm during reset upon reset the pwme bit is cleared. in effect, this disables the pwm system and configures the pc7/pwm pin as a high impedance port c input pin. the user should write to the data register prior to enabling the pwm system (for instance, prior to setting pwme). this avoids an erroneous duty cycle from being driven. 12.8 pwm power supply source the pwm is supplied by v dd and v ss , due to the noise generated by the digital circuitry, since this module is not affected by supply noise. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required pulse width modulator (pwm) general release specification MC68HC705CT4 rev. 2.0 98 pulse width modulator (pwm) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola comparators 99 non-disclosure agreement required general release specification MC68HC705CT4 section 13. comparators 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 13.3 comparator control/status register. . . . . . . . . . . . . . . . . . . .101 13.4 reading comparator outputs. . . . . . . . . . . . . . . . . . . . . . . . .103 13.5 comparator during wait mode . . . . . . . . . . . . . . . . . . . . . . . .103 13.6 comparator during stop mode. . . . . . . . . . . . . . . . . . . . . . . .103 13.7 comparator power supply source . . . . . . . . . . . . . . . . . . . . .103 13.2 introduction port d shares its pins with cmp3+/pd0, cmp1C/pd1 and cmp12+/pd2, cmp2C/pd3 of the comparators. the output of the comparators is a status bit internal to the mcu. this circuitry is used for the comparison of analog signals, with a digital output. the comparator circuitry may be powered up by setting the cen1, cen2, and the cen3 bits in the comparator control/status register. this register is located at $0022 and is cleared by reset. the state of the comparator output bit upon reset is logic 0. for further electrical information see section 17. electrical specifications . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required comparators general release specification MC68HC705CT4 rev. 2.0 100 comparators motorola figure 13-1. comparator block diagram voltage comparator 1 + C cmp1 pd1/ cen1 voltage comparator 2 + C cmp2 pd3/ pd2/ cen2 cmp1C cmp12+ cmp2C voltage comparator 3 + C cmp3 pd0/ internal cen3 ref cmp3+ cm3ie cmp3 int port d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . comparators comparator control/status register MC68HC705CT4 rev. 2.0 general release specification motorola comparators 101 non-disclosure agreement required 13.3 comparator control/status register cmp3 comparator 3 output this bit is implemented in two ways: as a real-time comparator output or as a latched interrupt source. the state of cm3ie determines which implementation is selected. cm3ie = 0 (nonlatched mode) this status bit is is cleared only by two means: 1. clearing cm3ie while the voltage at cmp3+ is less than cmp3C 2. by an external reset cm3ie = 1 (latched mode) this latched status bit is set when the voltage at cmp3+ (pd0) is larger than that of cmp3C (internal voltage reference ~ 2 v dd/ 3). an interrupt is then initiated ($1ffaC$1ffb). cmp2 comparator 2 output this status bit is set when the voltage at cmp12+ is larger than that of cmp2C, otherwise, it is cleared. reset clears this bit because the comparator is disabled. cmp1 comparator 1 output this status bit is set when the voltage at cmp12+ is larger than that of cmp1C, otherwise, it is cleared. reset clears this bit because the comparator is disabled. address: $0022 bit 7 654321 bit 0 read: cmp3 cmp2 cmp1 cm3ie 0 cen3 cen2 cen1 write: reset: 00000000 = unimplemented figure 13-2. comparator control/status register (cmpcsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required comparators general release specification MC68HC705CT4 rev. 2.0 102 comparators motorola cm3ie comparator 3 interrupt enable this control bit, when set, allows cmp3 to generate an interrupt when it goes high. cen3 comparator 3 enable this control bit, when set, powers up the voltage comparator 3 on pd0. the user must set this bit to allow any functionality of the comparator. after enabling the comparator, the user should delay for t cen before reading the state of the output or enabling the interrupt. reset clears this bit. pd0 remains under control of its ddr bit to enable the user to drive cmp3+ to a desired level. when cen3 is cleared, the comparator is disabled and consumes negligible power. cen2 comparator 2 enable this control bit, when set, powers up the voltage comparator 2 on pd2 and pd3. the user must set this bit to allow any functionality of the comparator. after enabling the comparator, the user should delay for t cen before reading the state of the output. reset clears this bit. pd2 and pd3 remain under control of their ddr bits to enable the user to drive cmp2C and cmp12+ to desired levels. when cen2 is cleared, the comparator is disabled and consumes negligible power. cen1 comparator 1 enable this control bit, when set, powers up voltage comparator 1 on pd1 and pd2. the user must set this bit to allow any functionality of the comparator. after enabling the comparator, the user should delay for t cen before reading the state of the output. reset clears this bit. pd1 and pd2 remain under control of their ddr bits to enable the user to drive cmp1C and cmp12+ to desired levels. when cen1 is cleared, the comparator is disabled and consumes negligible power. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . comparators reading comparator outputs MC68HC705CT4 rev. 2.0 general release specification motorola comparators 103 non-disclosure agreement required 13.4 reading comparator outputs the state of each comparator output bit is internally readable from the cmpcsr. 13.5 comparator during wait mode the comparator operates normally in wait mode. if the user wishes to save power during the wait mode, the cen1, cen2, and cen3 bits should be cleared before the wait instruction. 13.6 comparator during stop mode stop mode does not affect the comparator circuit. if the user needs to save power, the cen1, cen2, and cen3 bits should be cleared before the stop instruction. 13.7 comparator power supply source the comparators are supplied by v dd2 and v ss2 . these power lines are reserved for noise-susceptible circuitry, such as the circuitry found in the comparators. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required comparators general release specification MC68HC705CT4 rev. 2.0 104 comparators motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola miscellaneous register 105 non-disclosure agreement required general release specification MC68HC705CT4 section 14. miscellaneous register 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 14.3 miscellaneous control register . . . . . . . . . . . . . . . . . . . . . . .105 14.4 miscellaneous register power supply source . . . . . . . . . . . .106 14.2 introduction the miscellaneous register exists to hold various system control bits. it is located at address $0021. 14.3 miscellaneous control register speed cpu speed select this control bit, when set, selects an additional divide-by-eight after the already divide-by-five from the oscillator clock to the internal bus clock. this makes the internal cpu clock a divide-by-40 from the oscillator input. when clear, the internal bus clock is a divide-by-five from the oscillator input. reset clears this bit. address: $0021 bit 7 654321 bit 0 read: 0000 speed coe pwme 0 write: reset: 00000000 figure 14-1. miscellaneous control register (miscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required miscellaneous register general release specification MC68HC705CT4 rev. 2.0 106 miscellaneous register motorola coe 16-bit timer output compare enable this control bit, when set, enables the 16-bit output compare function to come out on pd6/tcmp. when clear, pd6 returns to a general- purpose i/o pin. pwme pwm enable this control bit, when set, enables the pwm function to come out on pc7/pwm. when clear, pc7 returns to a general-purpose i/o pin. 14.4 miscellaneous register power supply source the miscellaneous control register is supplied by v dd and v ss . v dd2 and v ss2 are reserved for noise-susceptible circuitry. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola eprom 107 non-disclosure agreement required general release specification MC68HC705CT4 section 15. eprom 15.1 contents 15.2 introduction .............................................................................107 15.3 eprom...................................................................................107 15.4 bootloader mode ....................................................................108 15.4.1 bootloader functions ........................................................108 15.4.2 programming register ......................................................112 15.4.3 mask option register........................................................114 15.2 introduction this section describes erasable programmable read-only memory (eprom) programming. 15.3 eprom the user eprom consists of 5120 bytes of eprom from $0b00 to $1eff and 16 bytes of user vectors from $1ff0 to $1fff. the bootloader rom and vectors are located from $1f01 to $1fef. twelve of the user vectors, $1ff4 thorough $1fff, are dedicated to reset and interrupt vectors. the four remaining locations, $1ff0, $1ff1, $1ff2 and $1ff3, are general-purpose user eprom locations. location $1f00 is the mask option register (mor). the contents of the eprom cannot be prevented from being viewed externally, since security is not incorporated into the MC68HC705CT4. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required eprom general release specification MC68HC705CT4 rev. 2.0 108 eprom motorola 15.4 bootloader mode bootloader mode is entered upon the rising edge of reset if the irq is at v tst and the pb1 pin is at logic 1. the bootloader code resides in the rom from $1f01 to $1fef. this program handles copying of user code from an external eprom into the on-chip eprom. the bootload function does not have to be done from an external eprom, but it may be done from a host. the user code must be a one-to-one correspondence with the internal eprom addresses. note: the mcu designer must disable the cop hardware in bootloader mode. 15.4.1 bootloader functions three pins are used to select various bootloader functions: pb0, pb3, and pb4. pb0 is normally a sync pin, which is used to synchronize the mcu to an off-chip source driving eprom data into the mcu. if an external eprom is used, this pin must be connected to v ss . pb4 and pb3 are used to select a programming mode. two other pins, pc2 and pc3, are used to drive the prog led and the verf led, respectively. the programming modes, along with gate and drain stress, are shown in table 15-1 . the bootloader uses an external 12-bit counter to address the memory device containing the code to be copied. this counter requires a clock and a reset function. the 12-bit counter can address up to 4 kbytes of table 15-1. bootloader functions pb0 pb4 pb3 mode sync 1 1 program/verify sync 1 0 verify only sync 0 0 dump eprom 0 0 1 gate stress 1 0 1 drain stress f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom bootloader mode MC68HC705CT4 rev. 2.0 general release specification motorola eprom 109 non-disclosure agreement required memory, which means that a port pin has to be used to address the extra memory space. figure 15-1. programmer interface to host data out port a clk (out) sync (in) host read data (a) dump eprom interface to a host clk (out) sync (in) data in (b) program/verify interface to a host data read f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required eprom general release specification MC68HC705CT4 rev. 2.0 110 eprom motorola figure 15-2. MC68HC705CT4 bootloader flowchart boot pb2 = 0 jump to ram put ramsub in ram ddrc ? %00001111 portc ? %00001111 get byte from port a program byte jsr nxtadr gate stress drain stress ddra = output get byte start @ $b00 put byte on port a change instruction from sta to eor inc count to $b00 start addr ? $b00 get byte from port a jsr ramsub jsr nxtadr end address ($1fff) end address ($1fff) wait wait pb0=1 (sync) wait verf led on compare end addr ($1fff) pb4 = 1 pb3 = 1 pb4 = 1 pb0 = 1 yes yes no yes no yes yes yes yes yes yes no no no no no no no no yes dump eprom prg/verf verify mayprg bump count to $b00 bump count to $b00 ddrb ? %00100000 portb ? %00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom bootloader mode MC68HC705CT4 rev. 2.0 general release specification motorola eprom 111 non-disclosure agreement required figure 15-3. MC68HC705CT4 programming circuit v dd v dd a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 clk rst pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 mc14040b d0 d1 d2 d3 d4 d5 d6 d7 osc1 osc2 reset pb0 (sync) pc2 pc3 pc1 pc0 irq/v pp prog verf 2764 ce oe pb5 pb3 pb4 pb2 v dd v dd v dd v dd v pp 15 pf 10 m w 10.24 mhz 15 pf 10 9 8 7 6 5 4 3 25 24 21 23 2 9 7 6 5 3 2 4 13 12 14 15 1 11 10 11 12 13 15 16 17 18 19 20 22 note: all resistors are 10 k w unless specified otherwise. 390 w 390 w v dd 16 8 v ss v dd 14 28 27 1 pb1 v dd pd5 mc74hc02 2 3 5 6 8 9 11 13 10 4 1 14 7 v dd 12 v ss2 v dd2 v dd2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required eprom general release specification MC68HC705CT4 rev. 2.0 112 eprom motorola 15.4.2 programming register this register is used to program the eprom array. only the latch and epgm bits are available in user mode. to program a byte of eprom, set latch, write data to the desired address, and then set epgm for t epgm. eptst, mbe, ts1, and ts0 are available only in the special modes, boot and test. moron mor on read: only in special modes, user mode returns a logic 0 write: only in special modes 1 = enables the decode to the mor register latch. this feature makes production testing and emulation easier. it is only valid when iooff is cleared to zero. 0 = the mor register is not in the map; intselb is not pulled at $1f00. eptst eprom test mode enable read: only in special modes, user mode returns a logic 0 write: only in special modes 1 = enables the functions of ts1 and ts0. 0 = ts1 and ts0 functions are disabled. address: $0011 bit 7 654321 bit 0 read: moron eptst mbe ts1 ts0 latch 0 epgm write: reset: 00000000 figure 15-4. programing register (prog) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom bootloader mode MC68HC705CT4 rev. 2.0 general release specification motorola eprom 113 non-disclosure agreement required mbe multiple byte program enable read: only in special modes, user mode returns a logic 0 write: only in special modes 1 = enable the multibyte programming, two bytes at a time. address bit 4 is dont care so that the bytes with addresses 5 = 0 and 5 = 1 are both programmed. 0 = normal programming ts1 and ts0 eprom test select bits read: only in special modes, user mode returns a logic zero write: only in special modes latch eprom latch control read: any time write: any time 0 = eprom address and data bus configured for normal reads 1 = eprom address and data bus configured for programming. causes address and data bus to be latched when a write to eprom is done. eprom cannot be read if latch = 1. epgm eprom program control read: any time write: cleared any time, set only if latch = 1 0 = programming power switched off the eprom array 1 = programming power switched on to the eprom array. if latch = 0, then epgm is cleared automatically. epgm cannot be set if latch is not set. latch and epgm cannot both be set on the same write. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required eprom general release specification MC68HC705CT4 rev. 2.0 114 eprom motorola 15.4.3 mask option register the mask option register, mor, contains programmable eprom bits to control mask options. the mor register is latched upon reset going away. pcxpu port c pullup (x is 7C4) when set, the pcpu bit enables the pullup on the corresponding port c pin. if the pcpu bit is cleared, the pullup devices are disabled. the erased state of the pcpu bit is to be cleared, thereby disabling the pullup devices. pc23pu port c bit 2 and 3 pullups when set, the pc23pu bit enables the pullups on both port c bits 2 and 3. if the pc23pu bit is cleared, the pullup devices are disabled. the erased state of the pc23pu bit is to be cleared, thereby disabling the pullup devices. pc01pu port c bit 0 and 1 pullups when set, the pc01pu bit enables the pullups on both port c bits 0 and 1. if the pc01pu bit is cleared, the pullup devices are disabled. the erased state of the pc01pu bit is to be cleared, thereby disabling the pullup devices. cop cop enable when set, this bit enables the cop watchdog timer. when clear, the cop is disabled. address: $1f00 bit 7 654321 bit 0 read: pc7pu pc6pu pc5pu pc4pu pc23pu pc01pu irq cop write: reset: 00000000 figure 15-5. mask option register (mor) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom bootloader mode MC68HC705CT4 rev. 2.0 general release specification motorola eprom 115 non-disclosure agreement required irq irq sensitivity when set, this bit selects the edge- and level-sensitive irq. when clear, it selects the edge-only-sensitive irq. in test mode, reading and writing the mor is done according to table 15-2 . table 15-2. mor read/write based on mode and latch bit latch test read write 00en pe = program eprom byte r = register latch n = nothing e = eprom byte 1 0npe 01er 1 1rpe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required eprom general release specification MC68HC705CT4 rev. 2.0 116 eprom motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 117 non-disclosure agreement required general release specification MC68HC705CT4 section 16. instruction set 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 16.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 16.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 16.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 16.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 16.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 16.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 16.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 16.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 16.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 16.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 16.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . .122 16.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . .123 16.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . .124 16.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .126 16.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 16.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705CT4 rev. 2.0 118 instruction set motorola 16.2 introduction the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 16.3 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: ? inherent ? immediate ? direct ? extended ? indexed, no offset ? indexed, 8-bit offset ? indexed, 16-bit offset ? relative f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set addressing modes MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 119 non-disclosure agreement required 16.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 16.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 16.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 16.3.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705CT4 rev. 2.0 120 instruction set motorola 16.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000C$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 16.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000C$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 16.3.7 indexed,16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 121 non-disclosure agreement required 16.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of C128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch. 16.4 instruction types the mcu instructions fall into the following five categories: ? register/memory instructions ? read-modify-write instructions ? jump/branch instructions ? bit manipulation instructions ? control instructions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705CT4 rev. 2.0 122 instruction set motorola 16.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 16-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 123 non-disclosure agreement required 16.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value. table 16-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) bit set bset (1) clear register clr complement (ones complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705CT4 rev. 2.0 124 instruction set motorola 16.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from C128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 125 non-disclosure agreement required table 16-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705CT4 rev. 2.0 126 instruction set motorola 16.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 16-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 127 non-disclosure agreement required 16.4.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 16-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705CT4 rev. 2.0 128 instruction set motorola 16.5 instruction set summary table 16-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 129 non-disclosure agreement required bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 table 16-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705CT4 rev. 2.0 130 instruction set motorola clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) C (m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ? ( m) = $ff C (m) a ? ( a) = $ff C (a) x ? ( x) = $ff C (x) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) C (m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 16-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 131 non-disclosure agreement required jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? effective address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 16-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705CT4 rev. 2.0 132 instruction set motorola ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) C (m) C (c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) C (m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 table 16-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary MC68HC705CT4 rev. 2.0 general release specification motorola instruction set 133 non-disclosure agreement required tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) C $00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow ?ag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry ?ag z zero ?ag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative ?ag set or cleared n any bit not affected table 16-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general release specification MC68HC705CT4 rev. 2.0 134 instruction set motorola instruction set table 16-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola electrical specifications 135 non-disclosure agreement required general release specification MC68HC705CT4 section 17. electrical specifications 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 17.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 17.4 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 17.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 17.6 5.0 v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . .138 17.7 3.3 v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . .139 17.8 3.3 v and 5.0 v control timing. . . . . . . . . . . . . . . . . . . . . . . .140 17.9 comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 17.10 pwm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 17.11 pll signal input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 17.2 introduction this section contains the electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical specitcations general release specification MC68HC705CT4 rev. 2.0 136 electrical specifications motorola 17.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guaranteed to operate properly at the maximum ratings. refer to 17.6 5.0 v dc electrical characteristics and 17.7 3.3 v dc electrical characteristics for guaranteed operating conditions. rating symbol value unit supply voltage v dd C0.3 to +7.0 v input voltage v in v ss C0.3 to v dd + 0.3 v bootloader mode ( irq pin only) v in v ss C0.3 to 2 x v dd + 0.3 current drain per pin excluding v dd and v ss i25ma operating junction temperature t j +150 c storage temperature range t stg C65 to +150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications operating range MC68HC705CT4 rev. 2.0 general release specification motorola electrical specifications 137 non-disclosure agreement required 17.4 operating range 17.5 thermal characteristics characteristic symbol value unit operating temperature range MC68HC705CT4 (standard) t a t l to t h 0 to +70 c characteristic symbol value unit thermal resistance plastic dual in-line package q ja 70 c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical specitcations general release specification MC68HC705CT4 rev. 2.0 138 electrical specifications motorola 17.6 5.0 v dc electrical characteristics characteristic symbol min typ max unit output voltage i load = 10.0 m a i load = C10.0 m a v ol v oh v dd C0.1 0.1 v output high voltage (i load -C0.8 ma) port a, port b, port c, port d v oh v dd C0.8 v output low voltage (i load = 1.6 ma) port a, port b, port c, port d v ol 0.4 v input high voltage port a, port b, port c, port d, irq, re3.5set, osc1 v ih 0.7 x v dd v dd v input low voltage port a, port b, port c, port d, irq, reset, osc1 v il v ss 0.3 x v dd v input hysteresis tcap, reset, irq, pd4/sck v hyst 0.8 0.9 1 v eprom programming voltage v pp 14.5 15.5 v supply current (see notes) run wait stop 25 c 0 c to +70 c i dd 3 0.3 10 20 10 1 25 30 ma ma m a m a supply current (see notes) run wait stop 25 c 0 c to +70 c i dd2 1.5 0.5 200 250 3 1.3 300 350 ma ma m a m a i/o ports hi-z leakage current port a, port b, port d i oz 5 m a input current reset, irq, osc1 pc0Cpc7 with pullups enabled i in C20 C125 10 C250 m a capacitance ports (as input or output) reset, irq c out c int 12 8 pf notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. all values shown re?ect average measurements. 3. typical values at midpoint of voltage range, 25 c only 4. wait i dd and i dd2 : only timer system active. 5. run (operating) i dd , i dd2 , wait i dd , and i dd2 : measured using external square wave clock source (f osc = 10.24 mhz); all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 6. wait, stop i dd : all ports con?gured as inputs, v il = 0.2 v, v ih = v dd C0.2 v 7. stop i dd and i dd2 are measured with osc1 = v ss . 8. wait i dd and i dd2 are affected linearly by the osc2 capacitance. 9. run, wait, and stop i dd2 are measured directly off the v dd2 power supply. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3 v dc electrical characteristics MC68HC705CT4 rev. 2.0 general release specification motorola electrical specifications 139 non-disclosure agreement required 17.7 3.3 v dc electrical characteristics characteristic symbol min typ max unit output voltage i load = 10.0 m a i load = C10.0 m a v ol v oh v dd C0.1 0.1 v output high voltage (i load C0.2 ma) port a, port b, port c, port d v oh v dd C0.3 v output low voltage (i load = 1.6 ma) port a, port b, port c, port d v ol 0.3 v input high voltage port a, port b, port c, port d, irq, reset, osc1 v ih 0.7 x v dd v dd v input low voltage port a, port b, port c, port d, irq, reset, osc1 v il v ss 0.3 x v dd v eprom programming voltage v pp 14.5 15.5 v supply current (see notes) run wait stop 25 c 0 c to +70 c i dd 1.5 0.15 5 10 5 0.5 12 15 ma ma m a m a supply current (see notes) run wait stop 25 c 0 c to +70 c i dd2 0.5 0.3 100 125 2 0.8 150 175 ma ma m a m a i/o ports hi-z leakage current port a, port b, port d i oz 5 m a input current reset, irq, osc1 pc0Cpc7 with pullups enabled i in C20 C50 10 C125 m a capacitance ports (as input or output) reset, irq c out c int 12 8 pf notes: 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. all values shown re?ect average measurements. 3. typical values at midpoint of voltage range, 25 c only 4. wait i dd and i dd2 : only timer system active. 5. run (operating) i dd , i dd2 , wait i dd , and i dd2 : measured using external square wave clock source (f osc = 10.24 mhz); all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 6. wait, stop i dd : all ports con?gured as inputs, v il = 0.2 v, v ih = v dd C0.2 v 7. stop i dd and i dd2 are measured with osc1 = v ss . 8. wait i dd and i dd2 are affected linearly by the osc2 capacitance. 9. run, wait, and stop i dd2 are measured directly off the v dd2 power supply. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical specitcations general release specification MC68HC705CT4 rev. 2.0 140 electrical specifications motorola 17.8 3.3 v and 5.0 v control timing characteristic symbol min max unit frequency of operation crystal external clock f osc dc 10.24 10.24 mhz internal operating frequency crystal (f osc /5) external clock (f osc /5) f op dc 2.048 2.048 mhz cycle time t cyc 488 ns crystal oscillator startup time t oxov 100 ms stop recovery startup time (crystal oscillator) t ilch 100 ms reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) t ilih 125 ns interrupt pulse period t ilil (note 2) t cyc osc1 pulse width t oh ,t ol 90 ns eprom byte programming time t epgm 10.0 ms notes: 1. v dd = 3.0 to 5.5 vdc, v ss = 0 vdc, t a = 0 o c to +70 o c, unless otherwise noted 2. the minimum period t ilil , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 2t t cyc . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications comparators MC68HC705CT4 rev. 2.0 general release specification motorola electrical specifications 141 non-disclosure agreement required 17.9 comparators 17.10 pwm timing 17.11 pll signal input characteristic symbol min max unit input voltage range (see note 2) v int v ss C0.5 v dd +0.5 v voltage comparator propagation time measured at 100 mv overdrive (see note 3) t comp 10 m s common mode range (see note 4) v com v ss +1.5 v dd C0.5 v offset (see note 5) v off 20 mv comparator enable time (see note 6) t cen 100 ms input current v ss 2 v in v dd i in 1 m a input current v in v ss i in 4.0 ma gain bandwidth product 10 khz slew rate sr 5 v/ m s saturation voltage (i out = C5 ma) v sat 0.5 v internal voltage reference cmpC v ref x 90% x 110% (2/3) v dd notes: 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. the comparator is guaranteed to function over the speci?ed input voltage range with no erroneous outputs. 3. signal propagation time through the comparators measured with 100 mv of overdrive. 4. comparator is guaranteed to meet speci?cations; for example, sr, t comp , and v off. 5. input offset voltage is guaranteed over the temperature range. 6. enable time is the time from enabling the comparator with the cen bit until the comparator is fully functional. characteristic symbol min max unit pwm rise time t pwmr 15 35 ns pwm fall time t pwmr 15 35 ns characteristic symbol min max unit input voltage on fintx and finrx (peak-to-peak) v vco 200 mv p-p input frequency on fintx and finrx f vco 60 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical specitcations general release specification MC68HC705CT4 rev. 2.0 142 electrical specifications motorola figure 17-1. stop recovery timing diagram 1ffe 1ffe 1ffe 1ffe 1fff 4 t rl t ilih osc1 1 reset irq 2 irq 3 internal clock internal address bus t ilch 4064 t cyc notes: 1. represents the internal gating of the osc1 pin 2. irq pin edge-sensitive mask option 3. irq pin level- and edge-sensitive mask option 4. reset vector address shown for timing example reset or interrupt vector fetch f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola mechanical specifications 143 non-disclosure agreement required general release specification MC68HC705CT4 section 18. mechanical specifications 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 18.3 44-lead plastic-leaded chip carrier (case 777-02) . . . . . . .144 18.4 44-lead quad flat pack (case 824a-01) . . . . . . . . . . . . . . .145 18.2 introduction the MC68HC705CT4 is available in a 44-pin plastic-leaded chip carrier (plcc) and a 44-pin quad flat pack (qfp). package dimensions are provided in this section. the following figures show the latest package information at the time of this publication. to make sure that you have the latest package specifications, contact one of the following: ? local motorola sales office ? motorola fax back system (mfax?) C phone 1-602-244-6609 C email rmfax0@email.sps.mot.com; http://sps.motorola.com/mfax/ ? worldwide web (wwweb) home page at http://motorola.com/sps/ follow mfax or wwweb on-line instructions to retrieve the current mechanical specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required mechanical specitcations general release specification MC68HC705CT4 rev. 2.0 144 mechanical specifications motorola 18.3 44-lead plastic-leaded chip carrier (case 777-02) -n- -l- -m- d y d k v w 1 44 brk b z u x view d-d s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t g1 s l-m s 0.010 (0.25) n s t k1 f h s l-m m 0.007(0.180) n s t z g g1 r a e j view s c s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t 0.004 (0.10) -t- seating plane view s dim min max min max millimeters inches a 0.685 0.695 17.40 17.65 b 0.685 0.695 17.40 17.65 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.650 0.656 16.51 16.66 u 0.650 0.656 16.51 16.66 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 g1 0.610 0.630 15.50 16.00 k1 0.040 1.02 s l-m s 0.010 (0.25) n s t s l-m m 0.007(0.180) n s t 2 10 notes: 1. datums -l-, -m-, and -n- are determined where top of lead sholders exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimension r and u do not include mold flash. allowable mold flash is 0.010 (0.25) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of the mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. diminsion h does not include dambar protrusion or intrusion. the dambar protusion(s) shall not cause the h diminsion to be greater than 0.037 (0.940146). the dambar intrusion(s) shall not cause the h diminision to smaller than 0.025 (0.635). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 44-lead quad flat pack (case 824a-01) MC68HC705CT4 rev. 2.0 general release specification motorola mechanical specifications 145 non-disclosure agreement required 18.4 44-lead quad flat pack (case 824a-01) ! ! l -d- bv a s m c h -c- g m -h- -a- l detail a 33 23 34 44 22 12 111 -b- e b b -a,b,d- -h- j k m w d f n r t q base metal x section bb detail a detail c ) ) ) ) ) ) ) ) "! ! " ! ' " ! " "# (( ! " " "" ! " %" " % " &"! " !" ' " " "" " " "# ! (( (( (( " " " "# (( ! ! ! $ " " " !" (( ! ! " # " #! % " #! ! ! ! ! # ! " " " "# (( ! ! " # " #! % " #! ! " " &!! " ! " & # " " " " " % #! " " ! ! ! ! ! ! ! ! ! ! detail c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required mechanical specitcations general release specification MC68HC705CT4 rev. 2.0 146 mechanical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705CT4 rev. 2.0 general release specification motorola ordering information 147 non-disclosure agreement required general release specification MC68HC705CT4 section 19. ordering information 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 19.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 19.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .148 19.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . .149 19.6 rom verification units (rvus) . . . . . . . . . . . . . . . . . . . . . . .150 19.7 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 19.2 introduction this section contains instructions for ordering custom-masked rom mcus. 19.3 mcu ordering forms to initiate an order for a rom-based mcu, first obtain the current ordering form for the mcu from a motorola representative. submit the following items when ordering mcus: ? a current mcu ordering form that is completely filled out (contact your motorola sales office for assistance.) ? a copy of the customer specification if the customer specification deviates from the motorola specification for the mcu ? customers application program on one of the media listed in 19.4 application program media f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required ordering information general release specification MC68HC705CT4 rev. 2.0 148 ordering information motorola the current mcu ordering form is also available through the motorola freeware bulletin board service (bbs). the telephone number is (512) 891-free. after making the connection, type bbs in lower-case letters. then press the return key to start the bbs software. 19.4 application program media please deliver the application program to motorola in one of the following media: ? macintosh 1 3 1/2-inch diskette (double-sided 800 k or double-sided high-density 1.4 m) ? ms-dos 2 or pc-dos tm 3 3 1/2-inch diskette (double-sided 720 k or double-sided high-density 1.44 m) ? ms-dos or pc-dos tm 5 1/4-inch diskette (double-sided double- density 360k or double-sided high-density 1.2m) use positive logic for data and addresses. when submitting the application program on a diskette, clearly label the diskette with this information: ? customer name ? customer part number ? project or product name ? file name of object code ? date ? name of operating system that formatted diskette ? formatted capacity of diskette on diskettes, the application program must be in motorolas s-record format (s1 and s9 records), a character-based object file format generated by m6805 cross assemblers and linkers. 1. macintosh is a registered trademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft corporation. 3. pc-dos is a trademark of international business machines corporation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information rom program verification MC68HC705CT4 rev. 2.0 general release specification motorola ordering information 149 non-disclosure agreement required note: begin the application program at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all nonuser rom locations or leave all nonuser rom locations blank. refer to the current mcu ordering form for additional requirements. motorola may request pattern re-submission if nonuser areas contain any nonzero code. if the memory map has two user rom areas with the same address, then write the two areas in separate files on the diskette. label the diskette with both file names. in addition to the object code, a file containing the source code can be included. motorola keeps this code confidential and uses it only to expedite rom pattern generation in case of any difficulty with the object code. label the diskette with the file name of the source code. 19.5 rom program verification the primary use for the on-chip rom is to hold the customers application program. the customer develops and debugs the application program and then submits the mcu order along with the application program. motorola inputs the customers application program code into a computer program that generates a listing verify file. the listing verify file represents the memory map of the mcu. the listing verify file contains the user rom code and may also contain nonuser rom code, such as self-check code. motorola sends the customer a computer printout of the listing verify file along with a listing verify form. to aid the customer in checking the listing verify file, motorola will program the listing verify file into customer-supplied blank preformatted macintosh or dos disks. all original pattern media are filed for contractual purposes and are not returned. check the listing verify file thoroughly, then complete and sign the listing verify form and return it to motorola. the signed listing verify form constitutes the contractual agreement for the creation of the custom mask. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required ordering information general release specification MC68HC705CT4 rev. 2.0 150 ordering information motorola 19.6 rom verification units (rvus) after receiving the signed listing verify form, motorola manufactures a custom photographic mask. the mask contains the customers application program and is used to process silicon wafers. the application program cannot be changed after the manufacture of the mask begins. motorola then produces 10 mcus, called rvus, and sends the rvus to the customer. rvus are usually packaged in unmarked ceramic and tested to 5 vdc at room temperature. rvus are not tested to environmental extremes because their sole purpose is to demonstrate that the customers user rom pattern was properly implemented. the 10 rvus are free of charge with the minimum order quantity. these units are not to be used for qualification or production. rvus are not guaranteed by motorola quality assurance. 19.7 mc order numbers table 19-1 shows the mc order numbers for the available package types. table 19-1. mc order numbers mc order number operating temperature range MC68HC705CT4fn 0 c to 70 c MC68HC705CT4fb 0 c to 70 c note: fn = 44-lead plastic-leaded chip carrier fb = 44-lead quad flat pack f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc705ct4grs/d ? motorola, inc., 1997 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?cally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or speci?cations can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?cers, employees, subsidiaries, af?liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?rmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution, p.o. box 5405, denver, colorado 80217, 1-800-441-2447 or 1-303-675-2140. customer focus center, 1-800-521-6274 japan: nippon motorola ltd. spd, strategic planning of?ce 4-32-1, nishi-gotanda shinagawa-ku, tokyo 141, japan, 81-3-5487-8488 asia/pacific: motorola semiconductors h.k. ltd., 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong, 852-26629298 mfax?, motorola fax back system: rmfax0@email.sps.mot.com; http://sps.motorola.com/mfax/; touchtone, 1-602-244-6609; us and canada only, 1-800-774-1848 home page: http://motorola.com/sps/ mfax is a trademark of motorola, inc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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